Abstract
In this present work, we explore the hot carrier fidelity of gate electrode workfunction engineered silicon nanowire (GEWE-SiNW) MOSFET at 300 K using DEVEDIT-3D device editor and ATLAS device simulation software. TCAD simulation shows reduction in the hot carrier reliability of a GEWE SiNW MOSFET in terms of electron temperature, electron velocity and Hot Electron gate current for reflecting its efficacy in high power CMOS applications. Further, a comparative investigation for different values of oxide thickness and high-k has been done to analyze the performance of GEWE-SiNW MOSFET in terms of electrical parameters such as conduction band, DIBL, electric field, electron temperature, electric velocity and gate current. It has been clearly shown that with oxide thickness 0.5 nm the hot-carrier reliability and device performance improves in comparison to oxide thickness 2.5 nm. In addition, with k = 21(HfO2) device performance in terms of hot-carrier reliability further enhanced due to increased capacitance and thus offer its effectiveness in sub-nm range analog applications.
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Acknowledgments
The authors would like to thank the Microelectronics Research Lab, Department of Engineering Physics, Delhi Technological University (formerly DCE) and one of the authors (Neha Gupta) is grateful to the University Grant Commission (UGC) for providing the necessary financial assistance to carry out this research work.
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Gupta, N., Kumar, A. & Chaujar, R. Oxide bound impact on hot-carrier degradation for gate electrode workfunction engineered (GEWE) silicon nanowire MOSFET. Microsyst Technol 22, 2655–2664 (2016). https://doi.org/10.1007/s00542-015-2557-9
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DOI: https://doi.org/10.1007/s00542-015-2557-9