Design of 5.5 GHz linear low noise amplifier using post distortion technique with body biasing

Abstract

A highly linear 5.5 GHz low noise amplifier (LNA) has been designed exploiting source inductive degeneration topology by using post distortion linearization techniques in 0.18 m CMOS technology. This technique improves the input third order intercept point $(IIP_{3})$ of a low noise amplifier. For enhancing the linearity, this technique used a diode connected MOSFET as IMD sinker and forward body biased which is done in cadence tool. The proposed low noise amplifier achieves high $IIP_{3}$ by using two transistors, main and auxiliary transistors. Also source inductive degeneration topology is employed in the proposed LNA to optimize the noise figure (NF) and $S_{11}$ at high frequency. In order to reduce power consumption and threshold voltage, Forward Body Biased technique was implemented. In this paper, the first section discusses the most widely used eight linearization techniques and in the second section, the proposed circuit is represented along with its employed topology, techniques and the simulated results. The proposed LNA achieves a simulated third order input intercept $(IIP_{3})$ of 9.20 dBm while consuming 10.8 mW from a power supply of 1.8 V. it also exhibits a measured gain of 11.34 dB and NF, NF of 2.33 dB.