Abstract
This paper reports a method on the manufacturing of through silicon wafer via holes with tapered walls by Deep Reactive Ion Etching using the opportunity to change the isotropy in the DRIE equipments during processing. By using consecutively anisotropic and isotropic etching steps it is possible to enlarge the dimension of via holes on one side of the wafer, while on the other side dimension is set by the initial etching window. The optimized process was used to obtain via’s with a good control over the walls angles for two etching windows sizes (100 and 20 μm respectively) on 300 μm thick silicon wafers. After process optimization, a deviation smaller than 10% of the manufactured via holes across the wafers was observed for the designed walls angles of 11.3° and 21.8°. Barrier and seed layers were deposited in via’s performed by Physical Vapor Deposition techniques with a very good coverage of the walls. Finally, gold electroplating was used to fill the narrow part of via’s.
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References
Gassend BLP, Velásquez-García LF, Akinwande AI (2010) Design and fabrication of DRIE-patterned complex needlelike silicon structures. JMEMS 19(3):589–598
Hirose K, Shiraishi F, Mita Y (2007) A simultaneous vertical and horizontal self-patterning method for deep three-dimensional microstructures. J Micromech Microeng 17:S68–S76
Larmer F, Schilp A (1992) Method for anisotropically etching silicon. German Patent DE4241045
Larsen KP, Ravnkilde JT, Hansen O (2005) Investigations of the isotropic etch of an ICP source for silicon microlens mold fabrication. J Micromech Microeng 15:873–882
Li R, Lamy Y, Besling WFA, Roozeboom F, Sarro PM (2008) Continuous deep reactive ion etching of tapered via holes for three-dimensional integration. J Micromech Microeng 18(12):125023
Lietaer N, Storas P, Breivik L, Moe S (2006) Development of cost-effective high-density through-wafer interconnects for 3D Microsystems. J Micromech Microeng 16:S29–S34
Lin C-W, Yang H-A, Wang WC, Fang W (2007) Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections. J Micromech Microeng 17(6):1200–1205
Marty F, Rousseau L, Saadany B, Mercier B, Francais O, Mita Y, Bourouina T (2005) Advanced etching of silicon based on deep reactive ion etching for silicon high aspect ratio microstructures and three-dimensional micro- and nanostructures. Microelectron J 36:673–677
Polyakov A, Bartek M, Burghartz JN (2002) Mechanical reliability of silicon wafers with through-wafer vias for wafer-level packaging. Microelectron Reliab 42(9–11):1783–1788
Polyakov A, Grob T, Hovenkamp RA, Kettelarij HJ, Eidner I, de Samber MA, Bartek M, Burghartz JN (2004) Comparison of via-fabrication techniques for through-wafer electrical interconnect applications. In: Proceedings of 54th electronic components and technology conference, p 1466
Premachandran CS, Nagarajan R, Yu C, Xiolin B, Choong CS (2003) A novel electrically conductive wafer through hole filled vias interconnect for 3D MEMS packaging. In: Electronic components and technology conference, p 627
Shikida M, Inagaki N, Sasaki H, Amakawa H, Fukuzawa K, Sato K (2010) The mechanism of selective corrugation removal by KOH anisotropic wet etching. J Micromech Microeng 20:015038
Subbarao SN et al (1982) Method for fabricating via holes in a semiconductor wafer. 320 430, US Patent, 4 348 253
Wolf MJ, Dretschkow T, Wunderle B, Jürgensen N, Engelmann G, Ehrmann O, Uhlig A, Michel B, Reichl H (2008) High aspect ratio TSV copper filling with different seed layers. In: Proceedings of 58th electronic components and technology conference
Acknowledgments
The authors acknowledge the European Space Agency (MIGNON project ARTES 5.1–5C.091) for the support in this work.
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Vasilache, D., Colpo, S., Giacomozzi, F. et al. Through wafer via holes manufacturing by variable isotropy Deep RIE process for RF applications. Microsyst Technol 18, 1057–1063 (2012). https://doi.org/10.1007/s00542-012-1438-8
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DOI: https://doi.org/10.1007/s00542-012-1438-8