Abstract
The fabrication of microchannels using MEMS technology always attracted the attention of researchers and designers of microfluidic systems. Our group focused on realizing buried fluidic channels in silicon substrates involving deep reactive ion etching. To meet the demands of today’s complex microsystems, our aim was to create passive microfluidics in the bulk Si substrate well below the surface, while retaining planarity of the wafer. Therefore additional lithographic steps for e.g. integrating circuit elements are still possible on the chip surface. In this paper, a more economic process flow is applied which also contains a selective edge-masking method in order to eliminate under-etching phenomenon at the top of the trenches to be filled. The effect of Al protection on the subsequent etch steps is also discussed. Applying the proposed protection method, our group successfully fabricated sealed microchannels with excellent surface planarity above the filled trenches. Due to the concept, the integration of the technology in hollow silicon microprobes fabrication is now available.
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Acknowledgments
The authors would like to thank the staff of MEMS Laboratory, MTA-MFA for their precise contribution to this work. This work was partially supported by ENIAC JTI and the National Innovation Office (NIH) via CAJAL4EU project, the Hungarian National Research Fund (OTKA) via NF69262. The János Bolyai fellowship of the Hungarian Academy of Sciences is also gratefully acknowledged.
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Fekete, Z., Pongrácz, A., Fürjes, P. et al. Improved process flow for buried channel fabrication in silicon. Microsyst Technol 18, 353–358 (2012). https://doi.org/10.1007/s00542-012-1430-3
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DOI: https://doi.org/10.1007/s00542-012-1430-3