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Reliability study of hermetic wafer level MEMS packaging with through-wafer interconnect

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Abstract

In this paper, we developed a hermetic wafer level packaging for MEMS devices. Au–Sn eutectic bonding technology in a relatively low temperature is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of 1 mm × 1 mm × 700 μm, and a square loop Au–Sn metallization of 70 μm in width for hermetic sealing. The robustness of the package is confirmed by several tests such as shear strength test, reliability tests, and hermeticity test. The reliability issues of Au–Sn bonding technology, and copper through-wafer interconnection are discussed, and design considerations to improve the reliability are also presented. By applying O2 plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface. The mechanical effects of copper through-vias are also investigated numerically and experimentally. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, copper diffusion phenomenon, and cleaning process. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process.

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Acknowledgment

This work was supported by Joint Research Program “MCP Core Technologies for the Next Generation” from Ministry of Knowledge Economy in Korea.

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  1. Department of Nano/IT Engineering, Seoul National University of Technology, 172 Gongneung-2 Dong, Nowon-gu, Seoul, 139-743, Korea

    Sung-Hoon Choa

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  1. Sung-Hoon Choa
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Correspondence to Sung-Hoon Choa.

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Choa, SH. Reliability study of hermetic wafer level MEMS packaging with through-wafer interconnect. Microsyst Technol 15, 677–686 (2009). https://doi.org/10.1007/s00542-009-0788-3

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  • DOI: https://doi.org/10.1007/s00542-009-0788-3

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