Melanoma is the most dangerous form of skin cancer, which is responsible for the majority of skin cancer-related deaths. Early diagnosis of melanoma can significantly reduce mortality rates and treatment costs. Therefore, skin cancer specialists are using image-based diagnostic tools for detecting melanoma earlier. We aim to develop a handheld device featured with low cost and high performance to enhance early detection of melanoma at the primary healthcare. But, developing this device is very challenging due to the complicated computations required by the embedded diagnosis system. Thus, we aim to exploit the recent hardware technology in reconfigurable computing to achieve a high-performance embedded system at low cost. Support vector machine (SVM) is a common classifier that shows high accuracy for classifying melanoma within the diagnosis system and is considered as the most compute-intensive task in the system. In this paper, we propose a dynamic hardware system for implementing a cascade SVM classifier on FPGA for early melanoma detection. A multi-core architecture is proposed to implement a two-stage cascade classifier using two classifiers with accuracies of 98% and 73%. The hardware implementation results were optimized by using the dynamic partial reconfiguration technology, where very low resource utilization of 1% slices and power consumption of 1.5 W were achieved. Consequently, the implemented dynamic hardware system meets vital embedded system constraints of high performance and low cost, resource utilization, and power consumption, while achieving efficient classification with high accuracy.
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Saegusa T, Maruyama T, Yamaguchi Y (2008) How fast is an FPGA in image processing? Int Conf Field Program Log Appl FPL 2008:77–82
Hussain HM, Benkrid K, Seker H (2013) The role of FPGAs as high performance computing solution to bioinformatics and computational biology data. In: AIHLS2013, p 102
Asano S, Maruyama T, Yamaguchi Y (2009) Performance comparison of FPGA, GPU and CPU in image processing. In: International conference on field programmable logic and applications, 2009. FPL 2009, pp 126–131
Pietron M, Wielgosz M, Zurek D, Jamro E, Wiatr K (2013) Comparison of GPU And FPGA implementation of SVM algorithm for fast image segmentation. In: Architecture of computing systems–ARCS 2013, pp 292–302. Springer
Fykse E (2013) Performance comparison of GPU, DSP and FPGA implementations of image processing and computer vision algorithms in embedded systems. M.Sc. thesis, Department of Electronics and Telecommunications, Norwegian University of Science and Technology
Sasamal TN, Prasad R (2011) Module based and difference based implementation of partial reconfiguration on FPGA: a review. Int J Eng Res Appl (IJERA) 1:1898–1903
Sabouri P, GholamHosseini H, Larsson T, Collins J (2014) A cascade classifier for diagnosis of melanoma in clinical images. In: 36th annual international conference of the ieee engineering in medicine and biology society (EMBC), pp 6748–6751
Afifi SM, GholamHosseini H, Sinha R (2015) Hardware implementations of SVM on FPGA: a state-of-the-art review of current practice. Int J Innov Sci Eng Technol (IJISET) 2:733–752
Kyrkou C, Theocharides T, Bouganis C.-S (2013) An embedded hardware-efficient architecture for real-time cascade support vector machine classification. In: 2013 International conference on embedded computer systems: architectures, modeling, and simulation (SAMOS XIII), pp 129–136
Afifi S, GholamHosseini H, Sinha R (2017) SVM classifier on chip for melanoma detection. In: The 39th annual international conference of the IEEE engineering in medicine and biology society (EMBC’17)
Papadonikolakis M, Bouganis C.-S (2010) A novel FPGA-based SVM classifier. In: International conference on field-programmable technology (FPT), pp 283–286
Papadonikolakis M, Bouganis C (2012) Novel cascade FPGA accelerator for support vector machines classification. IEEE Trans Neural Netw Learn Syst 23:1040–1052
Kyrkou C, Bouganis C.-S, Theocharides T, Polycarpou MM (2015) Embedded hardware-efficient real-time classification with cascade support vector machines. In: IEEE transactions on neural networks and learning systems
Kyrkou C, Theocharides T, Bouganis CS (2013) A hardware-efficient architecture for embedded real-time cascaded support vector machines classification. In: proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI, pp 341–342
Kyrkou C, Theocharides T, Bouganis C.-S, Polycarpou M (2017) Boosting the hardware-efficiency of cascade support vector machines for embedded classification applications. In: International Journal of parallel programming, pp 1–27
Hussain HM, Benkrid K, Seker H (2013) Reconfiguration-based implementation of SVM classifier on FPGA for classifying microarray data. In: 2013 35th Annual international conference of the IEEE engineering in medicine and biology society (EMBC), pp 3058–3061
Hussain H, Benkrid K, Şeker H (2016) Novel dynamic partial reconfiguration implementations of the support vector machine classifier on FPGA. Turk J Electric Eng Comput Sci 24:3371–3387
Hussain HM, Benkrid K, Seker H (2015) Dynamic partial reconfiguration implementation of the SVM/KNN multi-classifier on FPGA for bioinformatics application. In: 37th Annual international conference of the IEEE engineering in medicine and biology society (EMBC), pp 7667–7670
Vivado High-Level Synthesis. Available: http://www.xilinx.com/products/design-tools/vivado/integration/esl-design.html
Zynq-7000 All Programmable SoC. Available: http://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html
Vivado Design Suite. Available: http://www.xilinx.com/products/design-tools/vivado.html
Ning M, Shaojun W, Yeyong P, Yu P (2014) Implementation of LS-SVM with HLS on Zynq. Int Conf Field Program Technol (FPT) 2014:346–349
Tsoutsouras V, Koliogeorgi K, Xydis S, Soudris D (2017) An exploration framework for efficient high-level synthesis of support vector machines: case study on ECG arrhythmia detection for Xilinx Zynq SoC. J Signal Proces Syst 1–21
Vivado Design Suite User guide, High-Level Synthesis. Available: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug902-vivado-high-level-synthesis.pdf
Joachims T (1999) Making large-scale SVM learning practical. In: Advances Kernel methods: support vector learning, B. Schölkopf and C. Burges and A. Smola (ed.): MIT Press
Afifi S, GholamHosseini H, Sinha R (2016) Hardware Acceleration of SVM-based classifier for melanoma images. In: Huang F, Sugimoto A (eds) Image and video technology—PSIVT 2015 workshops: RV 2015, GPID 2013, VG 2015, EO4AS 2015, MCBMIIA 2015, and VSWS 2015, Auckland, New Zealand, November 23-27, 2015. Revised Selected Papers. Springer International Publishing. Cham, pp 235–245
Afifi S, GholamHosseini H, Sinha R (2016) A low-cost FPGA-based SVM classifier for melanoma detection. In: IEEE-EMBS conferences on biomedical engineering and Sciences
Ago Y, Nakano K, Ito Y (2013) A classification processor for a support vector machine with embedded DSP slices and block RAMs in the FPGA. In: 2013 IEEE 7th international symposium on embedded multicore SoCs (MCSoC), pp 91–96
Berberich M, Doll K (2014) Highly flexible FPGA-architecture of a support vector machine. In: MPC-Workshop vol 45, pp 25–32
Kyrkou C, Theocharides T (2012) A parallel hardware architecture for real-time object detection with support vector machines. IEEE Trans Comput 61:831–842
Kyrkou C, Theocharides T (2009) SCoPE: towards a systolic array for SVM object detection. IEEE Embed Syst Lett 1:46–49
Conflict of interest
The authors declare that they have no conflict of interest.
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Afifi, S., GholamHosseini, H. & Sinha, R. Dynamic hardware system for cascade SVM classification of melanoma. Neural Comput & Applic 32, 1777–1788 (2020). https://doi.org/10.1007/s00521-018-3656-1
- Cascade classifier
- Embedded system