Abstract
WBG semiconductors promise a profound change in power conversion. Among several advantages, the high switching speed of WBG devices allows reducing the size of passive filters.
Based on this characteristic, Silicon Carbide (SiC) MOSFETs, an example of WBG devices, can execute very narrow (< 300 ns) pulse patterns. This can be used to create an additional pulse sequence at each edge of the fundamental PWM at the inverter output. This additional pulse pattern requires just a small LC filter and significantly reduces the dv/dt at the cable input and, thus, at the motor terminals. Faster SiC MOSFETs show less risk of unwanted oscillations, which may occur due to interlock-delay. Much slower Silicon (Si) IGBTs require interlock-delay during the same time period as the additional pulse patterns and, thus, an interlock-delay compensation to mitigate the overvoltage. After presenting the principle of this approach, called Active dv/dt filter (ADVDTF), and a method to determine the pulse pattern, this paper assesses the overvoltage at motor terminals connected to a long cable (150 m) with SiC MOSFETS without interlock-delay compensation. It presents the results of a simulation and of an experimental test with a 1200 V SiC MOSFET power stage.
Zusammenfassung
Der Einsatz von WBG-Halbleitern stellt einen grundlegenden Wandel in der Leistungselektronik in Aussicht. Neben etlichen anderen Vorteilen erlaubt die hohe Schaltgeschwindigkeit von WBG-Leistungshalbleitern, die Größe passiver Filter zu reduzieren.
Diese hohe Schaltgeschwindigkeit erlaubt den Einsatz von Siliziumkarbid(SiC)-MOSFETs, als Beispiel für WBG-Leistungshalbleiter, zur Erzeugung sehr kurzer (< 300 ns) Pulsmuster. Solche kurzen Pulsmuster können an jeder Flanke des ursprünglichen, niederfrequenten PWM-Signals eines Antriebsumrichters eingefügt werden. Damit wird der Aufwand von LC-Filtern signifikant verringert und als Resultat eine starke Reduktion des dU/dt am Eingang eines Motorkabels, und dementsprechend auch an den Motoranschlüssen, erreicht. Aufgrund der hohen Schaltgeschwindigkeit von SiC-MOSFETs ist das Risiko unerwünschter Schwingungen, die durch den Einfluss des Interlock-Delay entstehen können, reduziert. Das wesentlich langsamere Schaltverhalten von Silizium(Si)-IGBTs erfordert Interlock-Delay im Zeitbereich der bevorzugten zusätzlichen Pulsmuster und somit eine entsprechende Kompensation, um das Auftreten von Überspannungen an den Motoranschlüssen zu vermeiden. Nach Vorstellung des grundlegenden Prinzips dieser „Active dv/dt filter“ (ADVDTF) genannten Methode und eines Verfahrens zur Ermittlung dieser zusätzlichen Pulsmuster wird in diesem Artikel das Überspannungsverhalten an den Motoranschlüssen am Ende langer Kabel (150 m), unter Verwendung von SiC-MOSFETs ohne Kompensation des Interlock-Delay, präsentiert. Dabei werden die Ergebnisse einer Simulation und eines Tests an einem realen Inverter, aufgebaut mit 1200-V-SiC-MOSFETS, gegenübergestellt.
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Boulharts, H., Fehringer, R. & Lechat, D. Active dv/dt filter with SiC MOSFET—interlock-delay effect on the overvoltage at motor terminals. Elektrotech. Inftech. 140, 66–81 (2023). https://doi.org/10.1007/s00502-022-01118-w
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DOI: https://doi.org/10.1007/s00502-022-01118-w