e & i Elektrotechnik und Informationstechnik

, Volume 132, Issue 6, pp 274–281 | Cite as

A netlist-level fault-injection tool for FPGAs

  • Christian Fibich
  • Peter Rössler
  • Stefan Tauner
  • Herbert Taucher
  • Martin Matschnig


A fault-injection tool can be very interesting in context to safety-critical applications, e.g., to test fault-detection and avoidance mechanisms or simply to stress an application and analyze its behavior when faults occur. In this work, a fault-injection tool is presented which can be used to instrument an FPGA design with fault-injection logic on netlist level during the implementation phase and to inject faults during runtime afterwards. The proposed approach can be smoothly integrated into an industrial FPGA tool flow, supports devices from multiple FPGA vendors and is highly configurable in order to fit to the number of available FPGA logic resources. Differences to related approaches which are applied on either HDL- and netlist-level as well as on the FPGA configuration bitstream are described. Finally, some results are presented to prove the applicability of the proposed solution.


fault-injection FPGA safety stress test verification 

Ein Tool zur Injektion von Fehlern in FPGA-Designs auf Netzlisten-Ebene


Tools zur Fehlerinjektion können speziell im Kontext von sicherheitskritischen Applikationen hilfreich sein, um etwa Mechanismen zur Fehlererkennung und -vermeidung zu testen oder das Verhalten einer Applikation im Fehlerfall zu überprüfen. Diese Arbeit beschreibt ein derartiges Werkzeug, das es erlaubt, ein FPGA-Design mit Zusatzlogik zur Fehlerinjektion im Zuge der Implementierungsphase auf Netzlisten-Ebene zu instrumentieren und danach zur Laufzeit Fehler am FPGA einzustreuen. Das vorgestellte Tool fügt sich in einen industriellen FPGA Tool Flow ein, unterstützt Devices verschiedener FPGA-Hersteller und kann durch entsprechende Konfiguration an die verfügbaren FPGA-Ressourcen angepasst werden. Die Arbeit geht auf Unterschiede zu existierenden Lösungen ein, die auf HDL- oder Netzlisten-Ebene, aber auch direkt im FPGA-Konfigurations-Bitstream Fehler injizieren. Schlussendlich werden einige Implementierungsergebnisse präsentiert, welche die Sinnhaftigkeit des vorgestellten Ansatzes belegen.


Fehlerinjektion FPGA Safety Stresstest Verifikation 



The work described herein was done within the “Josef Ressel Center for Verification of Embedded Computing Systems” (VECS) which is funded by the Austrian Federal Ministry for Science and Research (BM:WFJ), managed by the Christian Doppler Research Association.


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Copyright information

© Springer Verlag Wien 2015

Authors and Affiliations

  • Christian Fibich
    • 1
  • Peter Rössler
    • 1
  • Stefan Tauner
    • 1
  • Herbert Taucher
    • 2
  • Martin Matschnig
    • 2
  1. 1.Institut für Embedded SystemsFachhochschule Technikum WienWienÖsterreich
  2. 2.Corporate Technology, Research Group Electronic DesignSiemens AG ÖsterreichWienÖsterreich

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