Skip to main content
Log in

Verification challenges of complex system-on-chip devices

Herausforderungen an die Verifikation komplexer System-on-Chips

  • Originalarbeiten
  • Published:
e & i Elektrotechnik und Informationstechnik Aims and scope Submit manuscript


In recent years rising complexity, shrinking silicon feature sizes, and reduced design cycles have posed new challenges on the verification of modern system-on-chip solutions. To tackle the issues caused by the rising complexity various design and verification languages, as well as methodologies and tools have been introduced. Likewise, new and better physical process models allow for improved simulation of both analog and digital designs. Finally, strict management plans are used to cope with the shrinking design and verification cycles. Despite all these efforts, however, many problems exist in industrial state-of-the-art processes and tools.

This article gives some insights and presents some lessons learned from the design and verification of a recent automotive microcontroller, a complex system-on-chip solution. Based on these findings, a new verification flow is proposed that closes an identified gap between pre-silicon and post-silicon verification.


Mit der steigenden Komplexität und immer kürzer werdenden Entwicklungszyklen ergeben sich neue Herausforderungen für die Verifikation von modernen, komplexen System-on-Chip-Lösungen. Neue Sprachen, Werkzeuge und Methoden sowie Design-Ansätze auf höherem Abstraktionsniveau, gepaart mit der Verwendung von IP-Cores, ermöglichen es, mehr Funktionalität rascher zu entwickeln. Kleinere Prozessgeometrien und bessere physikalische Simulationsmodelle erlauben es zudem, dies auch auf stets kleinerer Siliziumsfläche mit geringerem Energiebedarf zu realisieren. Der gesamte Entwurfs- und Verifikationsprozess wird durch stringente industrielle Prozessabläufe gelenkt und geleitet. Insbesondere durch das Wechselspiel digitaler und analoger Elemente können einzelne Probleme dennoch erst spät entdeckt werden.

Dieser Beitrag gibt Einsicht in die Verifikation moderner Mikrokontroller und zeigt, welche Lehren aus diesem Prozess gezogen werden konnten. Basierend auf diesen Erkenntnissen wird ein neuer Verifikations-Prozess vorgestellt, der eine festgestellte Lücke zwischen Pre- und Post-Silizium-Verifikation zu schließen versucht.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
EUR 32.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or Ebook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1.
Fig. 2.
Fig. 3.

Similar content being viewed by others


  1. Adir, A., Copty, S., Landa, S., Nahir, A., Shurek, G., Ziv, A., Meissner, C., Schumann, J. (2011): A unified methodology for pre-silicon verification and post-silicon validation. In Design, automation test in Europe exhibition, DATE (pp. 1–6). Available online at: doi:10.1109/DATE.2011.5763252.

    Google Scholar 

  2. Adir, A., Nahir, A., Shurek, G., Ziv, A., Meissner, C., Schumann, J. (2011): Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor. In 48th ACM/EDAC/IEEE design automation conference, DAC (pp. 569–574). Available online at:

    Google Scholar 

  3. Melani, M., D’Ascoli, F., Marino, C., Fanucci, L., Giambastiani, A., Rocchi, A., De Marinis, M., Monterastelli, A. (2006): An integrated flow from pre-silicon simulation to post-silicon verification. In Ph.D. research in microelectronics and electronics (pp. 205–208). Available online at: doi:10.1109/RME.2006.1689932.

    Google Scholar 

  4. Azaïs, F., Bernard, S., Bertrand, Y., Renovell, M. (2001): A low-cost BIST architecture for linear histogram testing of ADCs. J. Electron. Test., 17(2), 139–147. Available online at: doi:10.1023/A:1011173710479.

    Article  Google Scholar 

  5. Azaïs, F., Bernard, S., Bertrand, Y., Renovell, M. (2001): Implementation of a linear histogram BIST for ADCs. In Design, automation and test in Europe proceedings, DATE (pp. 590–595). New York: IEEE Press. Available online at:

    Google Scholar 

Download references


This work has been supported by Infineon Technologies Austria AG and by the publicly funded Josef Ressel Center for Verification of Embedded Computing Systems (VECS) managed by the Christian Doppler Gesellschaft (CDG).

Author information

Authors and Affiliations


Corresponding author

Correspondence to Martin Horauer.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Horauer, M., Widhalm, D., Tauner, S. et al. Verification challenges of complex system-on-chip devices. Elektrotech. Inftech. 132, 269–273 (2015).

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: