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Digital twin based FPGA implementation of FIR filter for multi-bit soft computing error detection and correction for industrial applications

Soft Computing volume 27, pages 4289–4306 (2023)Cite this article

Abstract

Digital filters are increasingly being used in signal processing areas. The soft errors present in these circuits are found to affect the reliability of the systems such as biomedical and space applications. In this work, fault-tolerant digital finite impulse response (FIR) filters are designed to have the same impulse response that process different input signals and multiple responses with constant input signals using the soft computing approaches. The soft computing approaches used in the proposed FIR filters are Bose–Chaudhuri–Hocquenghem (BCH) code for single error correction and double error correction. The performance of the proposed method is evaluated by considering different FIR filter tap configurations. The Questasim simulator has been used to validate the functionality of the designed modules using a Verilog HDL. The Xilinx Vivado HLx 2018.3 and Artix-7 xc7a200 and Virtex-4 XC4VLX80 FPGA devices have been used for synthesis and implementation. Significant savings up to 28.02% and 21.8%, 26.67% and 26.33% of different field programmable gate array (FPGA) architecture resources like Slices, LUTs, flip-flops, and LUTRAMs for the parallel filters having the same impulse response and different impulse responses, respectively, are achieved as compared to the triple modular redundancy method. The digital parallel FIR filters implemented with FPGA shows effectiveness in terms of correction of single and double errors by employing the BCH code, implementation cost, and protection.

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Funding

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Authors and Affiliations

  1. Department of ECE, Dhanekula Institute of Engineering and Technology, Vijayawada, India

    Chandrasekhar Savalam

  2. Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, India

    Venkata Nagaratna Tilak Alapati

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  1. Chandrasekhar Savalam
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  2. Venkata Nagaratna Tilak Alapati
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Contributions

Conceptualization was contributed by CS and VNTA; methodology was contributed by CS; software was contributed by CS; validation was contributed by CS; formal analysis was contributed by CS; investigation was contributed by CS; resources was contributed by CS; data curation was contributed by CS; writing—original draft preparation, was contributed by CS and VNTA; writing—review and editing, was contributed by VNTA and CS; visualization was contributed by CS; supervision was contributed by VNTA. All authors have read and agreed to the published version of the manuscript.

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Correspondence to Chandrasekhar Savalam.

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Communicated by Deepak kumar Jain.

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Savalam, C., Alapati, V.N.T. Digital twin based FPGA implementation of FIR filter for multi-bit soft computing error detection and correction for industrial applications. Soft Comput 27, 4289–4306 (2023). https://doi.org/10.1007/s00500-022-07371-7

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Keywords

  • BCH code
  • Digital filters
  • Error detection and correction
  • FIR filters
  • FPGA
  • Soft errors
  • Triple modular redundancy