Skip to main content

Digital twin based FPGA implementation of FIR filter for multi-bit soft computing error detection and correction for industrial applications


Digital filters are increasingly being used in signal processing areas. The soft errors present in these circuits are found to affect the reliability of the systems such as biomedical and space applications. In this work, fault-tolerant digital finite impulse response (FIR) filters are designed to have the same impulse response that process different input signals and multiple responses with constant input signals using the soft computing approaches. The soft computing approaches used in the proposed FIR filters are Bose–Chaudhuri–Hocquenghem (BCH) code for single error correction and double error correction. The performance of the proposed method is evaluated by considering different FIR filter tap configurations. The Questasim simulator has been used to validate the functionality of the designed modules using a Verilog HDL. The Xilinx Vivado HLx 2018.3 and Artix-7 xc7a200 and Virtex-4 XC4VLX80 FPGA devices have been used for synthesis and implementation. Significant savings up to 28.02% and 21.8%, 26.67% and 26.33% of different field programmable gate array (FPGA) architecture resources like Slices, LUTs, flip-flops, and LUTRAMs for the parallel filters having the same impulse response and different impulse responses, respectively, are achieved as compared to the triple modular redundancy method. The digital parallel FIR filters implemented with FPGA shows effectiveness in terms of correction of single and double errors by employing the BCH code, implementation cost, and protection.

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15

Data availability

Enquiries about data availability should be directed to the authors.


  • Abdulhay E, Elamaran V, Arunkumar N et al (2018) Fault-tolerant medical imaging system with quintuple modular redundancy (QMR) configurations. J Ambient Intell Human Comput.

    Article  Google Scholar 

  • Afzaal U, Lee JA (2020) Trading the reliability of approximate TMR in FPGAs with the cost of mitigation. In: 23rd Euromicro conference on digital system design (DSD), Kranj, Slovenia, pp 660–663.

  • Babic I, Miljkovic A, Cabarkapa M, Nikolic V, Đorđevic A, Ranđelovic M, Ranđelovic D (2021) Triple modular redundancy optimization for threshold determination in intrusion detection systems. Symmetry 13(4):557.

    Article  Google Scholar 

  • Baumann R (2005) Soft errors in advanced computer systems. IEEE Des Test Comput 22(3):258–266

    Article  Google Scholar 

  • Benites LAC, Kastensmidt FL (2018) Automated design flow for applying triple modular redundancy (TMR) in complex digital circuits. In: IEEE 19th Latin-American test symposium (LATS), Sao Paulo, Brazil, pp 1–4.

  • Chouhan SS, Kaul A, Singh UP (2018) Soft computing approaches for image segmentation: a survey. Multimed Tools Appl 77:28483–28537.

    Article  Google Scholar 

  • El Saddik A (2018) Digital twins: The convergence of multimedia technologies. IEEE Multimed 25(2):87–92

    Article  Google Scholar 

  • Gambhir S, Malik S, Kumar Y (2016) Role of soft computing approaches in healthcare domain: a mini review. J Med Syst.

    Article  Google Scholar 

  • Gao Z, Yang W, Chen X, Zhao M, Wang J (2012) Fault missing rate analysis of the arithmetic residue codes-based fault-tolerant FIR filter design. In: Proceedings IEEE international on-line testing symposium (IOLTS), pp 130–133

  • Gao Z, Reviriego P, Pan W, Xu Z, Zhao M, Wang J, Maestro JA (2015) Fault tolerant parallel filters based on error correction codes. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(2):384–387

    Article  Google Scholar 

  • Gao Z, Zhu J, Yan T, Ullah A, Reviriego P (2021) Fault tolerant polyphase filters-based decimators for SRAM-based FPGA implementations. IEEE Trans Emerg Top Comput.

    Article  Google Scholar 

  • Hitana T, Deb AK (2004) Bridging concurrent and non-concurrent error detection in FIR filters. In: Proceedings of Norchip conference, pp 75–78

  • Huang YH (2010) High-efficiency soft-error-tolerant digital signal processing using fine-grain subword-detection processing. IEEE Trans Very Large Scale Integr (VLSI) Syst 18(2):291–304

    Article  Google Scholar 

  • Jiang Y, Yin S, Li K, Luo H, Kaynak O (2021) Industrial applications of digital twins. Philos Trans R Soc A 379(2207):20200360

    Article  Google Scholar 

  • Jin Y, Huan Y, Chu H, Zou Z, Zheng L (2018) TMR group coding method for optimized SEU and MBU tolerant memory design. In: IEEE international symposium on circuits and systems (ISCAS), Florence, Italy, pp 1–5.

  • Lin S, Costello DJ (2004) Error control coding, 2nd edn. Prentice-Hall, Englewood Cliffs

    MATH  Google Scholar 

  • Mitra S, Zhang M, Seifert N, Mak T, Kim KS (2007) Built-in soft error resilience for robust system design. In: Proceedings of 2007 IEEE international conference on integrated circuit design and technology, Austin, pp 1–6

  • Moya B, Badias A, Alfaro I, Chinesta F, Cueto E (2020) Digital twins that learn and correct themselves. Int J Numer Methods Eng.

    Article  Google Scholar 

  • Nahavandi S (2019) Industry 5.0—a human-centric solution. Sustainability 11(16):4371

    Article  Google Scholar 

  • Nicolaidis M (2005) Design for soft error mitigation. IEEE Trans Device Mater Reliab 5(3):405–418

    Article  Google Scholar 

  • Nieuwland AK, Jasarevic S, Jerin G (2006) Combinational logic soft error analysis and protection. In: Proceedings of 12th IEEE international on-line testing symposium (IOLTS'06), Lake Como, pp 6–12

  • Oppenheim AV, Schafer RW (1999) Discrete time signal processing, 2nd edn. Prentice-Hall, Upper Saddle River

    MATH  Google Scholar 

  • Pontarelli S, Cardarilli GC, Re M, Salsano A (2008) Totally fault-tolerant RNS based FIR filters. In: Proceedings of IEEE international on-line testing symposium (IOLTS), pp 192–194

  • Rebaudengo M, Reorda MS, Violante M (2004) A new approach to software-implemented fault tolerance. J Electron Test 20:433–437

    Article  MATH  Google Scholar 

  • Reddy A, Banarjee P (1990) Algorithm-based fault detection for signal processing applications. IEEE Trans Comput 39(10):1304–1308

    Article  Google Scholar 

  • Reviriego P, Bleakley CJ, Maestro JA (2011) Structural DMR: a technique for implementation of soft-error-tolerant FIR filters. IEEE Trans Circuits Syst II Express Briefs 58(8):512–516

    Google Scholar 

  • Reviriego P, Pontarelli S, Bleakley C, Maestro JA (2012) Area efficient concurrent error detection and correction for parallel filters. IET Electron Lett 48(20):1258–1260

    Article  MATH  Google Scholar 

  • Samudrala PK, Ramos J, Katkoori S (2004) Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs. IEEE Trans Nucl Sci 51(5):2957–2969

    Article  Google Scholar 

  • Santhiya M, Saranya S, Vijayachitra S, Lavanya CB, Rajarajeswari M (2021) Application of voter insertion algorithm for fault management using triple modular redundancy (TMR) technique. In: 2021 Third international conference on intelligent communication technologies and virtual mobile networks (ICICV), pp 578–583.

  • Shim B, Shanbhag N (2006) Energy-efficient soft error-tolerant digital signal processing. IEEE Trans Very Large Scale Integr (VLSI) Syst 14(4):336–348

    Article  Google Scholar 

  • Shivakumar P, Kistler M, Keckler SW, Burger D, Alvisi L (2002) Modeling the effect of technology trends on the soft error rate of combinational logic. In: Proceedings of international conference on dependable systems and networks, Washington DC, pp 389–398

  • Tsiatouhas Y, Haniotakis T, Nikolos D, Efstathiou C (2001) Concurrent detection of soft errors based on current monitoring. In: Proceedings of 7th international on-line testing workshop, Taormina, Italy, pp 106–110

  • Verdouw C, Tekinerdogan B, Beulens A, Wolfert S (2021) Digital twins in smart farming. Agric Syst 189:103046

    Article  Google Scholar 

  • Xu X, Lu Y, Vogel-Heuser B, Wang L (2021) Industry 4.0 and Industry 5.0—Inception, conception and perception. J Manuf Syst 61:530–535

    Article  Google Scholar 

  • Zhang M, Shanbhag NR (2004) A soft error rate analysis (SERA) methodology. In: Proceedings IEEE/ACM international conference on computer aided design ICCAD-2004, San Jose, pp 111–118

Download references


This research received no external funding.

Author information

Authors and Affiliations



Conceptualization was contributed by CS and VNTA; methodology was contributed by CS; software was contributed by CS; validation was contributed by CS; formal analysis was contributed by CS; investigation was contributed by CS; resources was contributed by CS; data curation was contributed by CS; writing—original draft preparation, was contributed by CS and VNTA; writing—review and editing, was contributed by VNTA and CS; visualization was contributed by CS; supervision was contributed by VNTA. All authors have read and agreed to the published version of the manuscript.

Corresponding author

Correspondence to Chandrasekhar Savalam.

Ethics declarations

Conflict of interest

The authors declare that they have no conflict of interest.

Informed consent

Not Applicable.

Additional information

Communicated by Deepak kumar Jain.

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Savalam, C., Alapati, V.N.T. Digital twin based FPGA implementation of FIR filter for multi-bit soft computing error detection and correction for industrial applications. Soft Comput 27, 4289–4306 (2023).

Download citation

  • Accepted:

  • Published:

  • Issue Date:

  • DOI:


  • BCH code
  • Digital filters
  • Error detection and correction
  • FIR filters
  • FPGA
  • Soft errors
  • Triple modular redundancy