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A 9-bit pseudo-noise-based calibrated successive approximation ADC with differential/integral nonlinearity enhancement

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Abstract

Analog to digital converters is becoming crucial in every electronically operated device. Though the functional specifications are setting higher thresholds as the architectures of the ADC are old. The successive approximation register (SAR) type analog to digital converter (ADC) is the optimal ADC architecture for both power and speed computations. Additional calibrations are required to avoid intricate converter designs for attaining the growing demands. In this paper, a 9-Bit SAR ADC with pseudo-noise injection calibration algorithm with capacitive digital to analog converter (DAC) is simulated using MATLAB to compensate for static errors. The designed ADC shows 72.3 dB spurious-free dynamic range (SFDR) after calibration with improved integral non-linearity (INL) and differential non-linearity (DNL) from − 16/+ 20 to ± 0.84 and − 1.2/+ 3.2 to ± 0.38 LSB, respectively. The circuit with desired specifications is modelled by using cadence virtuoso semiconductor laboratory 0.18 µm process design kit (PDK). The design reduces the utilization of complex architectures of ADC by utilizing additional circuitry.

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Authors and Affiliations

  1. Department of ECE, SR University, Warangal, Telangana, India

    Chakradhar Adupa

  2. Department of ECE, GITAM University, Visakhapatnam, Andhra Pradesh, India

    Chakradhar Adupa, Chaithanya Mannepalli & Sreenivasa Rao Ijjada

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  1. Chakradhar Adupa
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  2. Chaithanya Mannepalli
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  3. Sreenivasa Rao Ijjada
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Correspondence to Chakradhar Adupa.

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Adupa, C., Mannepalli, C. & Ijjada, S.R. A 9-bit pseudo-noise-based calibrated successive approximation ADC with differential/integral nonlinearity enhancement. Soft Comput 26, 4289–4294 (2022). https://doi.org/10.1007/s00500-021-06419-4

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