Abstract
Rapid growth of very large-scale integration (VLSI) technologies has achieved integrating millions of transistors into a single chip. This integration into a single chip results in complex circuitry, and hence, it is required to have minimal cost and low complex power estimation approaches. Power estimation of VLSI circuits at an initial stage is most prominent because it increases the life and stability of the circuit. In this work, a modified version of extreme learning machine (ELM) neural network called as adaptive wavelet extreme learning machine neural network model (AWELM) is developed and integrated with a designed fuzzy inference system (FIS) for computing power in respect of standard International Symposium on Circuits and Systems 1989 (ISCAS 1989) benchmark circuits. The proposed method is devised to estimate the power accurately for the complementary metal oxide semiconductor VLSI circuits. The developed method does not require prior knowledge about the circuit architecture and its connections. The new AWELM-FIS technique developed in this paper estimates the power in the circuit based on the input and output information and various data of gates pertaining to VLSI circuit itself. The developed method is investigated for its validity and effectiveness by comparing it with the existing methods reported in earlier literature studies, and to train the new model, the results presented in the literature of ISCAS 1989 have been employed. Results prove the effectiveness of newly proposed AWELM-FIS approach over all other compared methods from the existing literatures.
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References
Beikahmadi M, Mirabbasi S, Iniewski KK (2015) Design and analysis of a low-power readout circuit for CdZnTe detectors in 0.13-µm CMOS. IEEE Sens J 16(4):903–911
Bhuvana BP, Bhaaskaran VK (2018) A novel adiabatic logic for low power VLSI circuit design and power optimization using FinFET. In: VLSI design: circuits, systems and applications. Springer, Singapore, pp 117–126
Chakraverty M, Harisankar PS, Ruparelia V (2016) Low power design practices for power optimization at the logic and architecture levels for VLSI system design. In: 2016 international conference on energy efficient technologies for sustainability (ICEETS). IEEE, pp 727–733
Chang SY, Wu BC, Liou YL, Zheng RX, Lee PL, Chiueh TD, Liu TT (2019) An ultra-low-power dual-mode automatic sleep staging processor using neural-network-based decision tree. IEEE Trans Circuits Syst I Regul Pap 66(9):3504–3516
De BP, Kar R, Mandal D, Ghoshal SP (2016) An efficient design of CMOS comparator and folded cascode op-amp circuits using particle swarm optimization with an aging leader and challengers algorithm. Int J Mach Learn Cybern 7(2):325–344
Geetha BT, Padmavathi B, Perumal V (2017) Design methodologies and circuit optimization techniques for low power CMOS VLSI design. In: 2017 IEEE international conference on power, control, signals and instrumentation engineering (ICPCSI). IEEE, pp 1759–1763
Ilamathi K, Rangarajan P (2019) Intelligent computation techniques for optimization of the shortest path in an asynchronous network-on-chip. Cluster Comput 22(1):335–346
Jasmin M (2014) Optimization techniques for low power VLSI circuits. Middle-East J Sci Res 20(9):1082–1087
Kamaraj A, Anand IV, Marichamy P (2014) Design of low power combinational circuits using reversible logic and realization in quantum cellular automata. Int J Innov Res Sci Eng Technol 3(3):1449–1456
Katreepalli R, Haniotakis T (2019) Power efficient synchronous counter design. Comput Electr Eng 75:288–300
Khursheed A, Khare K, Haque FZ (2019) Designing of ultra-low-power high-speed repeaters for performance optimization of VLSI interconnects at 32 nm. Int J Numer Model Electron Netw Dev Fields 32(2):e2516
Kim J, Limotyrakis S, Yang CKK (2010) Multilevel power optimization of pipelined A/D converters. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(5):832–845
Kowsalya T, Palaniswami S (2016) Power reduction in very large scale integration circuit using spectral clustering-hierarchical mean cut clustering algorithm (SC-HMCC). J Comput Theor Nanosci 13(3):1694–1700
Li P, Tang H (2013) A low-power VLSI implementation for fast full-search variable block size motion estimation. Int J Electron 100(9):1240–1255
Maji KB, De BP, Kar R, Mandal D, Ghoshal SP (2019) CMOS analog amplifier circuits design using seeker optimization algorithm. IETE J Res. https://doi.org/10.1080/03772063.2019.1649207
Murthy GR, Senthilpari C, Velrajkumar P, Sze LT (2013) A novel design of multiplexer based full-adder cell for power and propagation delay optimizations. J Eng Sci Technol 8(6):764–777
Nallathambi G, Rajaram S (2014) A particle swarm optimization approach for low power very large scale integration routing. J Math Stat 10(1):58
Okuhara H, Ahmed AB, Kühn JM, Amano H (2018) Asymmetric body bias control with low-power FD-SOI technologies: modeling and power optimization. IEEE Trans Very Large Scale Integr (VLSI) Syst 26(7):1254–1267
Padmavathi B, Geetha BT, Bhuvaneshwari K (2017) Low power design techniques and implementation strategies adopted in VLSI circuits. In: 2017 IEEE international conference on power, control, signals and instrumentation engineering (ICPCSI). IEEE, pp 1764–1767
Rajeswari P, Chandra ST (2017) A survey on an optimal solution for VLSI circuit partitioning in physical design using DPSO & DFFA algorithms. In: 2017 international conference on intelligent sustainable systems (ICISS). IEEE, pp 868–872
Ramanathan P, Surendiran B, Vanathi PT (2013) Power estimation of benchmark circuits using artificial neural networks. Pensee 75(9):427–433
Rani VL, Latha MM (2016) Pass transistor-based pull-up/pull-down insertion technique for leakage power optimization in CMOS VLSI circuits. Circuits Syst Signal Process 35(11):4139–4152
Sasamal TN, Gaur HM, Singh AK, Mohan A (2020) Reversible circuit synthesis using evolutionary algorithms. In: Design and testing of reversible logic. Springer, Singapore, pp 115–128
Saxena V, Najm FN, Hajj IN (1997) Monte-Carlo approach for power estimation in sequential circuits. In: European design and test conference, (ED&TC 97), pp 416–420. https://doi.org/10.1109/edtc.1997.582393
Shea C, Page A, Mohsenin T (2018) SCALENet: a scalable low power accelerator for real-time embedded deep neural networks. In: Proceedings of the 2018 on great lakes symposium on VLSI. ACM, pp 129–134
Taassori M, Niroomand S, Uysal S, Hadi-Vencheh A, Vizvari B (2016) Fuzzy-based mapping algorithms to design networks-on-chip. J Intell Fuzzy Syst 31(1):27–43
Vellingiri G, Jayabalan R (2018) Adaptive neuro fuzzy inference system-based power estimation method for CMOS VLSI circuits. Int J Electron 105(3):398–411
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Kuntavai, T., Jeevanandham, A. Adaptive wavelet ELM-fuzzy inference system-based soft computing model for power estimation in sustainable CMOS VLSI circuits. Soft Comput 24, 11755–11768 (2020). https://doi.org/10.1007/s00500-019-04636-6
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DOI: https://doi.org/10.1007/s00500-019-04636-6