Abstract
This paper describes the application of evolutionary search to the problem of flash memory wear-out. Flash memory differs from standard RAM in that it can wear out due to the manner in which it is programmed. The operating parameters, such as voltage levels, of flash memory are notoriously difficult to determine, as the optimal values vary from batch to batch. The current method in use is an expensive and time-consuming manual process of destructive testing. Understandably, this process is normally undertaken only at design time and testing on individual batches is normally not feasible. The results are sub-optimum solutions which do not minimise wear-out over the lifetime of the device. This is an enormously important issue in manufacturing, as most Flash Memory devices requiring reliability (e.g. solid state device disk drives) often have 100% or more redundancy to compensate for the wear-out rates. We establish the viability of a hardware platform that utilises an Evolutionary Algorithm to perform destructive experimentation on hard silicon in order to discover optimal or, at least favourable, operating parameter settings automatically in a manufacturing environment. Here, we describe this hardware and reveal results demonstrating an average life extension of between 250 and 350% over the factory set conditions with a maximum life extension exhibited of 700% all for cells within the same device over the factory settings. Furthermore, since the process is automated, it is possible to leverage the spread between process batches to further enhance device specifications, facilitating the near no-cost life extension of a split-gate flash memory device.
Similar content being viewed by others
References
Aritome S, Shirota R, Hemink G, Endoh T, Masuoka F (1993) Reliability issues of flash memory cells. In: Proceedings of IEEE, pp 776–788
Bhattacharya S et al (1996) Improved performance and reliability of split gate source side injected flash memory cells. IEDM Tech Digest, pp 339–342
Fitzpatrick JM, Grefenstette JJ (1988) GAs in Noisy Environments Computer Science Department, Vanderbilt University, Nashville, Tennessee 37235
Forrest S, Mitchell M (1993) What makes a problem hard for a genetic algorithm? Some anomalous results and their explanation. Mach Learn 13:285–319
Fowler RH, Nordheim L (1928) Electron emission in intense electric fields. Proc R Soc Lond A119:172–81
Grefenstette JJ (1996) Optimization of control parameters for Genetic Algorithms. IEEE-SMC, SMC-16, 122–128
Goldberg DE (1989) Genetic Algorithms in search, optimization, and machine learning. Addison Wesley, Reading
Haddad S, Chang S, Swaminathan B, Lien J (1989) Degradation due to hole trapping in flash memory cells. IEEE Electr Device Lett 10:117–119
Haddad S, Chang S, Wang A, Bustillo J, Lien J, Montalvo T, Van Buskirk M (1990) An investigation of erase-mode dependent hole trapping in Flash EEPROM memory cell. IEEE Electron Device Lett 11:514–516
IEEE Std 1005 (1998) IEEE standard definitions and characterization of floating gate semiconductor arrays. The Institute of Electrical and Electronic Engineers, Inc, New York
Mohammad MG, Saluja KK, Yap AS (2000) Testing flash memories. In: 13th international conference on VLSI design, pp 406–411
Pavan P, Bez R, Olivo P, Zanomi E (1997) Memory cells—an overview. Proc IEEE 85(8):1248–1271
Reeves CR (1993) Using genetic algorithms with small population. In: Proceedings of the 5th international conference on Genetic Algorithms, Morgan Kaufmann, San Mateo
Sakui KO, Masuoka F (1990) Extended data retention characteristics after more than 10k write and erase cycles in EEPROMs, IEEE IRPS, pp 259–264
Silicon Storage Technology, Inc (1991) Technical comparison of floating gate reprogrammable nonvolatile memories. Silicon Storage Technology, Inc. 1171 Sonora Court, Sunnyvale. http://www.ssti.com
Tam S et al (1984) Lucky electron model of channel hot-electron injection in MOSFETs. IEEE transactions on electron devices, vol ED-31, pp 1116–1125
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Sullivan, J., Ryan, C. A destructive evolutionary algorithm process. Soft Comput 15, 95–102 (2011). https://doi.org/10.1007/s00500-009-0513-2
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00500-009-0513-2