Evaluation of CPU frequency transition latency

  • Abdelhafid Mazouz
  • Alexandre Laurent
  • Benoît Pradelle
  • William Jalby
Special Issue Paper


Dynamic Voltage and Frequency Scaling (DVFS) has appeared as one of the most important techniques to reduce energy consumption in computing systems. The main idea exploited by DVFS controllers is to reduce the CPU frequency in memory-bound phases, usually significantly reducing the energy consumption. However, depending on the CPU model, transitions between CPU frequencies may imply varying delays. Such delays are often optimistically ignored in DVFS controllers, whereas their knowledge could enhance the quality of frequency setting decisions.

The current article presents an experimental study on the measurement of frequency transition latencies. The measurement methodology is presented accompanied with evaluations on three Intel machines, reflecting three distinct micro-architectures. In overall, we show for our experimental setup that, while changing CPU frequency upward leads to higher transition delays, changing it downward leads to smaller or similar transition delays across the set of available frequencies.


DVFS Statistical performance evaluation Frequency transition latency 


  1. 1.
    Ge R, Feng X, Feng W-c, Cameron KW (2007) CPU MISER: a performance-directed, run-time system for power-aware clusters. In: ICPP 2007. International conference on parallel processing, p 18. doi:10.1109/ICPP.2007.29 CrossRefGoogle Scholar
  2. 2.
    Georges A, Buytaert D, Eeckhout L (2007) Statistically rigorous Java performance evaluation. In: Proceedings of the 22nd annual ACM SIGPLAN conference on object-oriented programming systems and applications (OOPSLA ’07). ACM, New York, pp 57–76. doi:10.1145/1297027.1297033 CrossRefGoogle Scholar
  3. 3.
    Hsu C-h, Feng W-c (2005) A power-aware run-time system for high-performance computing. In: Proceedings of the 2005 ACM/IEEE conference on supercomputing (SC ’05). IEEE Comput Soc, Washington, p 1. doi:10.1109/SC.2005.3 Google Scholar
  4. 4.
    Intel Corporation (2000) Developer manual: Intel 80200 processor based on Intel XScale datasheet Google Scholar
  5. 5.
    Intel Corporation (2000) How to benchmark code execution times on Intel IA-32 and IA-64 instruction set architectures. http://download.intel.com/embedded/software/IA/324264.pdf
  6. 6.
    Intel Corporation (2011) Intel Xeon processor E3-1200 family datasheet Google Scholar
  7. 7.
    Intel Corporation (2012) Intel Xeon processor E5-1600/E5-2600/E5-4600 product families Google Scholar
  8. 8.
    Intel Corporation (2013) Intel 64 and IA-32 architectures software developer’s manual: system programming guide. http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
  9. 9.
    Mazouz A, Touati SAA, Barthou D (2010) Study of variations of native program execution times on multi-core architectures. In: CISIS ’10: proc. of the international conference on complex, intelligent and software intensive systems (MuCoCos workshop). IEEE Comput Soc, Washington, pp 919–924. doi:10.1109/CISIS.2010.96 Google Scholar
  10. 10.
    Raj J (1991) The art of computer systems performance analysis: techniques for experimental design, measurement, simulation, and modelling. Wiley, New York Google Scholar
  11. 11.
    Snowdon D (2010) Operating system directed power management. PhD thesis, University of New South Wales Google Scholar
  12. 12.
    Mytkowicz T, Diwan A, Sweeney PF, Hauswirth M (2009) Producing wrong data without doing anything obviously wrong! In: Architectural support for programming languages and operating systems (ASPLOS) Google Scholar
  13. 13.
    Touati SAA, Worms J, Briais S (2012) The speedup-test: a statistical methodology for programme speedup analysis and computation. In: Concurrency and computation: practice and experience, p 22 Google Scholar
  14. 14.
    Wu Q, Martonosi M, Clark DW, Reddi VJ, Connors D, Wu Y, Lee J, Brooks D (2005) A dynamic compilation framework for controlling microprocessor energy and performance. In: MICRO, pp 271–282 Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Abdelhafid Mazouz
    • 1
  • Alexandre Laurent
    • 1
  • Benoît Pradelle
    • 1
  • William Jalby
    • 1
  1. 1.Univ. Versailles St-Quentin en YvelinesVersailles cedexFrance

Personalised recommendations