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Two-level hierarchical Z-buffer with compression technique for 3D graphics hardware

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Abstract

The hierarchical Z-buffer is application-invisible and more efficient than the traditional Z-buffer for quickly rejecting hidden geometries. But there are construction and management issues associated with integrating a hierarchical Z-buffer into current graphics hardware. Here we present a two-level hierarchical Z-buffer algorithm, and provide solutions to these issues. Simulation results show that the bandwidth can be reduced by up to 35%. Moreover we propose a dynamic bi-level HZ-buffer compression technique that reduces the buffer size up by to 40%, and for which there is little performance degradation.

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Authors and Affiliations

  1. Dept. of Electronics Engineering, National Chiao Tung University, 1001, Ta Hsueh Road, 300, R.O.C., Hsinchu, Taiwan

    Cheng-Hsien Chen & Chen-Yi Lee

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  1. Cheng-Hsien Chen
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  2. Chen-Yi Lee
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Correspondence to Cheng-Hsien Chen.

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Chen, CH., Lee, CY. Two-level hierarchical Z-buffer with compression technique for 3D graphics hardware. Vis Comput 19, 467–479 (2003). https://doi.org/10.1007/s00371-003-0212-4

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  • DOI: https://doi.org/10.1007/s00371-003-0212-4

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