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Impact of lateral straggle on linearity performance in gate-modulated (GM) TFET

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Abstract

Tunnel field effect transistor (TFET) is considered as a more viable device than MOSFET for low power applications. However, the performance of any device depends on the accuracy of the fabrication process. At the time of fabrication, the ion implantation technique extends the source/drain region toward the channel which affects the device performance. In this paper, we have highlighted the linearity performance of gate-modulated TFET (GM-TFET) by varying the lateral straggle parameter (σ) from 0 to 6 nm. The impact of σ on higher-order harmonics (gm2 and gm3), voltage intercept point (VIP2 and VIP3), input intercept power (IIP3), intermodulation distortion (IMD3), and 1 dB compression point is investigated to study the reliability and linearity of GM TFET.

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Acknowledgements

The authors acknowledge the funding by Science & Engineering Research Board (SERB), Govt. of India, (sanction order no SRG/2019/000628).

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Authors and Affiliations

  1. School of Electronics Engineering, Vellore Institute of Technology AP, Amravati, 522237, India

    Rajesh Saha

  2. Electronics and Communication Engineering, NIT Silchar, Silchar, Assam, India

    Brinda Bhowmick & Srimanta Baishya

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  1. Rajesh Saha
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Correspondence to Rajesh Saha.

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Saha, R., Bhowmick, B. & Baishya, S. Impact of lateral straggle on linearity performance in gate-modulated (GM) TFET. Appl. Phys. A 126, 201 (2020). https://doi.org/10.1007/s00339-020-3373-3

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