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Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis

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Abstract

The effects of stacked SiO2/HfO2 gate oxide, source pocket, and underlap gate engineering on the electrical and RF performances of cylindrical gate tunnel field-effect transistors (CGTFETs) have been investigated in this paper. While source pocket with underlap engineering reduces both the gate leakage current and subthreshold swing (SS), the stacked gate oxide improves the drain current of the CGTFET. The DC and RF performance parameters such as the electric field, drain current, transconductance, gate capacitance, unity gain cut-off frequency, gain–bandwidth product, transconductance frequency product, and intrinsic delay have been investigated for different stacked oxide CGTFETs with and without a source pocket as well as with and without an underlap structure. Our study demonstrates that the proposed underlapped stacked-oxide source-pocket engineered CGTFET structure not only enhances the drain current, but also improves the subthreshold switching characteristics of the device by reducing SS and gate leakage current.

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Authors and Affiliations

  1. IIT (BHU), Varanasi, Uttar Pradesh, India

    Prince Kumar Singh, Kamalaksha Baral, Sanjay Kumar, Sweta Chander, Manas Ranjan Tripathy, Ashish Kumar Singh & Satyabrata Jit

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  1. Prince Kumar Singh
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Singh, P.K., Baral, K., Kumar, S. et al. Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis. Appl. Phys. A 126, 166 (2020). https://doi.org/10.1007/s00339-020-3336-8

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