Skip to main content
SpringerLink
Log in

Investigation of N+ pocket-doped junctionless vertical TFET and its digital inverter application in the presence of true noises

  • Published:
Applied Physics A Aims and scope Submit manuscript

Abstract

This paper reports the investigation of conventional junctionless tunnel FET (JL-TFET) and N+ pocket-doped junctionless vertical tunnel FET (JL-VTFET). The investigation is done by analyzing the effect on the ID–VGS characteristics (a) under a wide range of temperature and (b) in the presence of acceptor interface trap charges. This work also examines the performance of noise and its impact on the digital inverter. Comparison has been made on the TCAD simulated results of both the devices. It is observed that the degradation of drain current (ID) is less in JL-VTFET and also it has better noise performance than that of conventional JL-TFET. Its net drain current noise spectral density (Sid) reaches 10–15 A2/Hz till 1 MHz and decreases with further increase in frequency. The contributions of generation–recombination noise and flicker noise are found to be more in low and moderate frequency, whereas diffusion noise dominates at high frequency. Furthermore, the impact of interface traps is studied using complementary JL-VTFET digital inverter application and compared with the one without interface traps. The transient characteristics show an average delay of 15 ps and 27 ps in the absence and presence of interface traps, respectively.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6:
Fig.7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. W.Y. Choi, B.-G. Park, J.D. Lee, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28, 743–745 (2007). https://doi.org/10.1109/LED.2007.901273

    Article  ADS  Google Scholar 

  2. A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy efficient electronic switches. Nature 479, 329–337 (2011)

    Article  ADS  Google Scholar 

  3. K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high-K gate dielectric. IEEE Trans. Electron Devices 54, 1725–1733 (2007)

    Article  ADS  Google Scholar 

  4. Y. Khatami, K. Banerjee, Steep subthreshold slope n- and p-type tunnel-FET devices for low-power and energy-efficient digital circuits. IEEE Trans. Electron Devices 56, 2752–2761 (2009)

    Article  ADS  Google Scholar 

  5. M.W. Amey, V. Anne, R. Rita, L. Daniele, H. Andriy, L. Roger, S.V. Anne, K. Kuo-Hsing, H. Cedric, G. Guido, R.R. Valipe, K.B. Krishna, M.H. Marc, C. Nadine, T. Aaron-Voon-Yew, Fabrication and analysis of a Si/Si0.55Ge0.45 heterojunction line tunnel FET. IEEE Trans. Electron Devices 61(3), 707–715 (2014)

    Article  Google Scholar 

  6. W.M. Reddick, G.A.J. Amaratunga, Silicon surface tunnel transistor. Appl. Phys. Lett. 67, 494–496 (1995). https://doi.org/10.1063/1.114547

    Article  ADS  Google Scholar 

  7. K.K. Bhuwalka, S. Sedlmaier, A.K. Ludsteck, Vertical tunnel field-effect transistor. IEEE Trans. Electron Devices 51, 279–282 (2004). https://doi.org/10.1109/TED.2003.821575

    Article  ADS  Google Scholar 

  8. G. Zhou, R. Li, T. Vasen, et al., Novel gate-recessed vertical InAs/GaSb TFETs with record high ION of 180 μA/μm at VDS = 0.5 V, in Proc. IEDM, San Francisco, pp. 777–780 (2012). https://doi.org/10.1109/IEDM.2012.6479154

  9. B. Ghosh, M.W. Akram, Junctionless tunnel field effect transistor. IEEE Electron Device Lett. 34(5), 584–586 (2013)

    Article  ADS  Google Scholar 

  10. S. Basak, P.K. Asthana, Y. Goswami et al., Leakage current reduction in junctionless tunnel FET using a lightly doped source. Appl. Phys. Lett. 118, 1527–1533 (2015). https://doi.org/10.1007/s00339-014-8935-9

    Article  Google Scholar 

  11. B.R. Raad, D. Sharma, P. Kondekar, K. Nigam, D.S. Yadav, Drain work function engineered doping-less charge plasma TFET for ambipolar suppression and RF performance improvement: a proposal, design, and investigation. IEEE Trans. Electron Devices 63(10), 3950–3957 (2016)

    Article  ADS  Google Scholar 

  12. M.A. Raushan, N. Alam, M.J. Siddiqui, Performance enhancement of junctionless tunnel field effect transistor using dual-k spacers. J. Nanoelectron. Optoelectron. 13, 1–9 (2018). https://doi.org/10.1166/jno.2018.2334

    Article  Google Scholar 

  13. S.B. Rahi, P. Asthana, S. Gupta, Heterogate junctionless tunnel field-effect transistor: future of low-power devices. J. Comput. Electron. 16, 30–38 (2016). https://doi.org/10.1007/s10825-016-0936-9

    Article  Google Scholar 

  14. W.V. Devi, B. Bhowmick, Optimisation of pocket doped junctionless TFET and its application in digital inverter. Micro Nano Lett (2018). https://doi.org/10.1049/mnl.2018.5086

    Article  Google Scholar 

  15. R. Bijesh, D.K. Mohata, H. Liu, S. Datta, Flicker noise characterization and analytical modeling of homo and hetero-junction III-V tunnel FETs. Proc. Device Res. Conf. (DRC) 37, 203–204 (2012). https://doi.org/10.1109/DRC.2012.6257032

    Article  Google Scholar 

  16. Sentaurus Device User: Synopsys (2009)

  17. R. Saha, B. Bhowmick, S. Baishya, Effects of temperature on electrical parameters in GaAs SOI FinFET and application as digital inverter, in Proc. Devices for Integrated Circuit (DevIC), pp 462–466 (2017)

  18. R. Pandey, B. Rajamohanan, H. Liu, V. Narayanan, S. Datta, Electrical noise in heterojunction interband tunnel FETs. IEEE Trans. Electron Devices 61, 552–560 (2014). https://doi.org/10.1109/TED.2013.2293497

    Article  ADS  Google Scholar 

  19. Q. Huang, R. Huang, C. Chen, C. Wu, J. Wang, C. Wang, et al., Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering, in Symposium on VLSI Technology: Digest of Technical Papers, pp. 70–71 (2014). https://doi.org/10.1109/VLSIT.2014.6894371

  20. A.P. Van Der Wel, E.M. Klumperink, J.S. Kolhatkar, E. Hoekstra, M.F. Snoeij, C. Salm, ET. AL., Low-frequency noise phenomena in switched MOSFETs. IEEE J. Solid-State Circuits 42, 540–549 (2007). https://doi.org/10.1109/JSSC.2006.891714

    Article  ADS  Google Scholar 

  21. M.V. Haartman, Low-frequency noise in advanced MOS devices. (2007). https://doi.org/10.1007/978-1-4020-5910-0

    Article  Google Scholar 

  22. J. Xu, J. Deen, MOSFET 1/f noise model based on mobility luctuation in linear region. Electron Lett. 38, 429–431 (2002). https://doi.org/10.1049/el:20020282

    Article  ADS  Google Scholar 

  23. S. Basak, P.K. Asthana, Y. Goswami, B. Ghosh, Leakage current reduction in junctionless tunnel FET using lightly doped source. Appl. Phys. A (2014). https://doi.org/10.1007/s00339-014-8935-9

    Article  Google Scholar 

  24. J. Madan, R. Chaujar, Temperature associated reliability issues of heterogeneous gate dielectric-gate all around-tunnel FET, in IEEE International Nanoelectronics Conference (INEC), Chengdu (2016). https://doi.org/10.1109/INEC.2016.7589278

  25. P. Ghosh, B. Bhowmick, Low-frequency noise analysis of heterojunction SELBOX TFET. Appl. Phys. A 124(838), 1–9 (2018)

    Google Scholar 

  26. W. Cao, C.J. Yao, G.F. Jiao, D. Huang, H. Yu, M.F. Li, Improvement in reliability of tunneling field-effect transistor with p-n-i-n structure. IEEE Trans. Electron Devices 58(7), 2122–2126 (2011)

    Article  ADS  Google Scholar 

  27. J. Madan, R. Chaujar, Numerical simulation of N+ source pocket PI-GAA-tunnel FET: impact of interface trap charges and temperature. IEEE Trans. Electron Devices 64(4), 1482–1488 (2017)

    Article  ADS  Google Scholar 

  28. R. Goswami, B. Bhowmick, S. Baishya, Electrical noise in circular gate tunnel FET in presence of interface traps. Superlattices Microstruct. 86, 342–354 (2015). https://doi.org/10.1016/j.spmi.2015.07.064

    Article  ADS  Google Scholar 

  29. R. Goswami, B. Bhowmick, S. Baishya, Effect of scaling on noise in circular gate TFET and its application as a digital inverter. Microelectron. J. 53, 16–24 (2016)

    Article  Google Scholar 

Download references

Acknowledgements

This publication is an outcome of the R&D work undertaken in the project under the Visvesvaraya PhD Scheme of Ministry of Electronics & Information Technology, Government of India, being implemented by Digital India Corporation (formerly Media Lab Asia).

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, Assam, 788010, India

    Vandana Devi Wangkheirakpam, Brinda Bhowmick & Puspa Devi Pukhrambam

Authors
  1. Vandana Devi Wangkheirakpam
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Brinda Bhowmick
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Puspa Devi Pukhrambam
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Vandana Devi Wangkheirakpam.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Wangkheirakpam, V.D., Bhowmick, B. & Pukhrambam, P.D. Investigation of N+ pocket-doped junctionless vertical TFET and its digital inverter application in the presence of true noises. Appl. Phys. A 126, 798 (2020). https://doi.org/10.1007/s00339-020-03983-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s00339-020-03983-8

Keywords

Search

Navigation