Skip to main content
SpringerLink
Log in

Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate

  • Published:
Applied Physics A Aims and scope Submit manuscript

Abstract

This paper reports the TCAD based investigation of the DC/RF and linearity characteristics of a newly proposed dual-material (DM) laterally-stacked (LS) SiO2/HfO2 heterojunction-TFET-on-SELBOX substrate (LS-STFET). Device-level performance comparison is made between the proposed TFET with a dual-material (DM) vertically-stacked (VS) SiO2/HfO2 heterojunction-TFET-on-SELBOX substrate (VS-STFET). Low bandgap material Ge is used in the source region to form a Ge (source)/Si (channel) heterojunction for enhancing the ON-state current of the presented TFETs. The effects of both donor (+ ve) and acceptor (−ve) type interface trap charges at the channel/SiO2 region on the DC, analogue/RF and linearity figure of merits have been analyzed for both the devices under study. The LS-STFET is shown to possess higher ON-state current and smaller subthreshold swing (SS) over the VS-STFET. In addition, the LS-STFET is shown to have better DC, analog/RF and linearity performance over VS-STFET in the presence of the donor and acceptor interface trap charges.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1.
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

References

  1. C.W. Pearce, D.S. Yaney, Shorts-channel effects in MOSFETs. IEEE. Electron. Device. Lett. 6(7), 326–328 (1985)

    Article  ADS  Google Scholar 

  2. Y. Taur, H. Chen, W. Wang, S. Lo, C. Wann, On–off charge-voltage characteristics and dopant number fluctuation effects in junctionless double-gate MOSFETs. IEEE. Trans. Electron. Devices. 59(3), 863–866 (2012)

    Article  ADS  Google Scholar 

  3. J. Jafar et al., Silicon nanowire field effect transistor sensors with minimal sensor-to-sensor variations and enhanced sensing characteristics. ACS Nano 7, 6577–6587 (2018)

    Google Scholar 

  4. J. Bethoux, H. Happy, G. Dambrine, J. Borghetti, V. Derycke, M. Coffman, J. P Bourgoin, Carbon nanotube field-effect transistor for GHz operation. In: 2006 Eur Solid-State Device Research Conference, Montreux, 206–209 (2006). https://doi.org/10.1109/ESSDER.2006.307674

  5. J.C. Wong, S. Salahuddin, Negative capacitance transistors. Proc IEEE 107(1), 49–62 (2019)

    Article  Google Scholar 

  6. A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011). https://doi.org/10.1038/nature10679

    Article  ADS  Google Scholar 

  7. W.Y. Choi, B.-G. Park, J.D. Lee, T.-J.K. Liu, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE. Electron. Device. Lett. 28(8), 743–745 (2007)

    Article  ADS  Google Scholar 

  8. M.R. Tripathy et al., Device and circuit-level assessment of GaSb/Si heterojunction vertical tunnel-FET for low-power applications. IEEE. Trans. Electron. Devices. 67(3), 1285–1292 (2020)

    Article  ADS  Google Scholar 

  9. A.K. Singh et al., Investigation of DC, RF and linearity performances of a back-gated (BG) heterojunction (HJ) TFET-on-selbox-substrate (STFET): Introduction to a BG-HJ-STEFT based CMOS inverter. Microelectron. J. 102, 104775 (2020). https://doi.org/10.1016/j.mejo.2020.104775

    Article  Google Scholar 

  10. D. Gracia, D. Nirmal, D.J. Moni, Impact of leakage current in germanium channel based DMDG TFET using drain-gate underlap technique. AEU. Int. J. Electron. Commun. 96, 164–169 (2018). https://doi.org/10.1016/j.aeue.2018.09.024

    Article  Google Scholar 

  11. A. K. Singh, M. R. Tripathy, K. Baral, P. K. Singh and S. Jit, Ferroelectric gate heterojunction TFET on selective buried oxide (SELBOX) substrate for distortionless and low power applications. In: 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), (Penang, Malaysia, pp 1-4) (2020). https://doi.org/10.1109/EDTM47692.2020.9117858

  12. P.K. Singh et al., Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis. Appl. Phys. A. 126, 166 (2020). https://doi.org/10.1007/s00339-020-3336-8

    Article  ADS  Google Scholar 

  13. M. R. Narayanan, H. Al-Nashash, B. Mazhari, D. Pal, Studies and minimization of kink effect in SOI MOSFET devices with SELBOX structure. In: 2008 International Conference on Microelectronics, (Sharjah, pp 232–235) (2008). https://doi.org/10.1109/ICM.2008.5393502

  14. A. K. Singh, M. R. Tripathy, S. Chander, K. Baral K, P. K. Singh, S. Jit, Simulation Study and Comparative Analysis of Some tfet Structures with a Novel Partial-Ground-Plane (PGP) Based TFET on SELBOX Structure. (Silicon, pp 1–10) (2019). https://doi.org/10.1007/s12633-019-00330-2.

  15. D. Barah, A. K. Singh, B. Bhowmik, TFET on Selective Buried Oxide (SELBOX) Substrate with Improved ION/IOFF Ratio and Reduced Ambipolar Current. (Silicon, pp 973–981) (2019). https://doi.org/10.1007/s12633-019-00330-2.

  16. S. Kumar, K.S. Singh, K. Nigam et al., Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance. Appl. Phys. A 125, 353 (2019). https://doi.org/10.1007/s00339-019-2650-5

    Article  ADS  Google Scholar 

  17. M.R. Tripathy et al., Impact of heterogeneous gate dielectric on DC, RF and circuit-level performance of source-pocket engineered Ge/Si heterojunction vertical TFET. Semicond. Sci. Technol. (2020). https://doi.org/10.1088/1361-6641/aba418

    Article  Google Scholar 

  18. L. Cong, Y.Z. Rui, Z.Y. Qi, Z.X. Long, G.J. Min, Ge/Si heterojunction L-shape tunnel field-effect transistors with hetero-gate-dielectric. Chin. Phys. B 27(7), 078502 (2018)

    Article  ADS  Google Scholar 

  19. ATLAS, Device Simulator Software, (SILVACO Int, Santa Clara, CA, USA, 2013)

    Google Scholar 

  20. M. Singh, S. Mishra, S.S. Mohanty, G.P. Mishra, Performance analysis of SOI MOSFET with rectangular recessed channel. Adv. Nat. Sci. Nanosci. Nanotechnol. 7(1), 015010 (2016)

    Article  ADS  Google Scholar 

  21. A. K. Singh, M. R. Tripathy, P. K. Singh, K. Baral, S. Chander and S. Jit, DC and RF Performance Optimization of Strained Si/Si1-xGex Heterojunction SOI P-TFET. In: 2018 15th IEEE India Council International Conference (INDICON), (Coimbatore, India, pp 1–5). https://doi.org/10.1109/INDICON45594.2018.8987144

  22. S. Shekhar, J. Madan, R. Chaujar, Source/gate material-engineered double gate TFET for improved RF and linearity performance: a numerical simulation. Appl. Phys. A. 124, 11 (2018). https://doi.org/10.1007/s00339-018-2158-4

    Article  Google Scholar 

  23. Y. Qiu, R. Wang, Q. Huang, R. Huang, A comparative study on the impacts of interface traps on tunneling FET and MOSFET. IEEE. Trans. Electron. Devices. 61(5), 1284–1291 (2014)

    Article  ADS  Google Scholar 

  24. B.V. Chandan, K. Nigam, D. Sharma, S. Pandey, Impact of interface trap charges on dopingless tunnel FET for enhancement of linearity characteristics. Appl. Phys. A. 124, 503 (2018). https://doi.org/10.1007/s00339-018-1923-8

    Article  ADS  Google Scholar 

  25. A. Pon, K.S.V.P. Tulasi, R. Ramesh, Effect of interface trap charges on the performance of asymmetric dielectric modulated dual short gate tunnel FET. AEU. Int. J. Electron. Commun. 102, 1–8 (2019). https://doi.org/10.1016/j.aeue.2019.02.007

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. IIT(BHU), Varanasi, Uttar Pradesh, India

    Ashish Kumar Singh, Manas Ranjan Tripathy, Kamalaksha Baral, Prince Kumar Singh & Satyabrata Jit

Authors
  1. Ashish Kumar Singh
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Manas Ranjan Tripathy
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Kamalaksha Baral
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Prince Kumar Singh
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Satyabrata Jit
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Satyabrata Jit.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Singh, A.K., Tripathy, M.R., Baral, K. et al. Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate. Appl. Phys. A 126, 681 (2020). https://doi.org/10.1007/s00339-020-03869-9

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s00339-020-03869-9

Keywords

Search

Navigation