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Design and analysis of dual-gate misalignment on the performance of dopingless tunnel field effect transistor

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Abstract

The submitted work presents a designed and analyzed dopingless double-gate tunnel field effect transistor. In the designed dopingless structure, doping is introduced by charge plasma technique and silicon is used as a choice of material. Initially, gate misalignment was done by shifting the bottom gate away from the drain region and toward the drain region by 50% and 100% amount. Further, both gates (top and bottom) have been misaligned by 50% and 100% for analyzing the device for analog and linearity performance. Analog parameters, device parameters and linearity parameters were calculated in order to understand the device behavior. By misaligning gates, it is found that when the bottom gate is shifting away from the source region, both gates have been misaligned by 100% showing that analog and linearity performance of the devices degrades. When the bottom gate is shifted toward the source, both gates have been misaligned by 50% providing better analog and linearity performance. Among all the misaligned structures, when both gates have been misaligned by 50% gives the best result such as ON-state current, OFF-state current, ION/IOFF, and subthreshold slope are 2.3 µA, 5.07 aA, 4.5 × 1011 and 32 mV/decade respectively.

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  1. VLSI Lab, Department of Electronics and Communications, Dr. B. R. Ambedkar, National Institute of Technology, Jalandhar, 144011, India

    Deep Shekhar & Ashish Raman

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  1. Deep Shekhar
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Shekhar, D., Raman, A. Design and analysis of dual-gate misalignment on the performance of dopingless tunnel field effect transistor. Appl. Phys. A 126, 441 (2020). https://doi.org/10.1007/s00339-020-03615-1

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