Applied Physics A

, 124:342 | Cite as

A new design approach for enhancement of DC/RF characteristics with improved ambipolar conduction of charge plasma TFET: proposal, and optimization

  • Mohd. Aslam
  • Dheeraj Sharma
  • Shivendra Yadav
  • Deepak Soni
  • Varun Bajaj
Article
  • 41 Downloads

Abstract

This article presents a new device structure to suppress ambipolarity with enhanced electrostatic characteristics of charge plasma TFET (CP-TFET). Here, implantation of a metal angle (MA) of low workfunction inside the high-k dielectric (HfO\(_{2}\)) layer near source/channel interface gives excellent improvement in DC and RF characteristics of the proposed device. Deposition of MA is advantageous to increase abruptness of source/channel junction for reducing the tunneling barrier. Along with MA placement, the metal electrode, which is placed over the silicon wafer for inducing N\(^{+}\) drain region, is divided into the two parts of low and high workfunctions. The workfunction of the part of metal electrode near the channel region is taken comparatively higher than the other part to restrict the tunneling of holes at drain/channel junction under negative bias (\(-V_\mathrm{gs}\)) condition. Such concept induces asymmetrical concentration of charge carriers in the drain region, which widens the tunneling barrier at the drain/channel interface. Consequently, the proposed device shows better RF performance along with suppressed ambipolar conduction. Furthermore, reliability of conventional and proposed structures has been tested in terms of linearity. Simultaneously, the effect of workfunction and length variation of MA on the device characteristics is analyzed in optimization section of the article.

Notes

Acknowledgements

The authors would like to thank the Science and Engineering Research Board, Department of Science and Technology, Government of India (established through an act of parliament) for providing the financial support to carry out this work. As this work has been implemented under the project “Implementation of Sigma Delta Modulator Using Nanowire Electrically Doped Hetero Material Tunnel Field Effect Transistor (TFET) for Ultra Low Power Applications” which is funded by this board.

References

  1. 1.
    J.-P. Colinge, FinFETs and Other Multi-Gate Transistors (Springer, New York, 2008)CrossRefGoogle Scholar
  2. 2.
    M.J. Kumar, S. Janardhanan, Doping-less tunnel field effect transistor: design and investigation. IEEE Trans. Electron Devices 60(10), 3285–3290 (2013)ADSCrossRefGoogle Scholar
  3. 3.
    V. Vijayvargiya, S.K. Vishvakarma, Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance. IEEE Trans. Nanotechnol. 13(5), 974–981 (2014)ADSCrossRefGoogle Scholar
  4. 4.
    R. Jhaveri, V. Nagavarapu, J.C.S. Woo, Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans. Electron Devices 58(1), 80–86 (2011)ADSCrossRefGoogle Scholar
  5. 5.
    S.O. Koswatta, M.S. Lundstrom, D.E. Nikonov, Performance comparison between p-i-n tunneling transistors and conventional MOSFETs. IEEE Trans. Electron Devices 56(3), 456–465 (2007)ADSCrossRefGoogle Scholar
  6. 6.
    W.Y. Choi, B.G. Park, J.D. Lee, T.J.K. Liu, Tunneling field-effect transistor (TFETs) with subthreshold swing (SS) less than 60 mV/Dec. IEEE Electron Device Lett. 28(8), 743–745 (2007)ADSCrossRefGoogle Scholar
  7. 7.
    U.E. Avci, D.H. Morris, I.A. Young, Tunnel field-effect transistors: prospects and challenges. IEEE J Electron Devices Soc. 3(3), 88–95 (2015)CrossRefGoogle Scholar
  8. 8.
    A.C. Seabaugh, Q. Zhang, Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98(12), 2095–2110 (2010)CrossRefGoogle Scholar
  9. 9.
    N. Damrongplasit, C. Shin, S.H. Kim, R.A. Vega, T.J.K. Liu, Study of random dopant fluctuation effects in germanium-source tunnel FETs. IEEE Trans. Electron Devices 58(10), 3541–3548 (2011)ADSCrossRefGoogle Scholar
  10. 10.
    A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479(7373), 329–337 (2011)ADSCrossRefGoogle Scholar
  11. 11.
    K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high-k gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007)ADSCrossRefGoogle Scholar
  12. 12.
    R.J.E. Hueting, B. Rajasekharan, C. Salm, J. Schmitz, Charge plasma p-n diode. IEEE Electron Device Lett. 29(12), 1367–1368 (2008)ADSCrossRefGoogle Scholar
  13. 13.
    B. Rajasekharan, R.J.E. Hueting, C. Salm, T. van Hemert, R.A.M. Wolters, J. Schmitz, Fabrication and characterization of the charge-plasma diode. IEEE Electron Device Lett. 31(6), 528–530 (2010)ADSCrossRefGoogle Scholar
  14. 14.
    B.R. Raad, S. Tirkey, D. Sharma, P. Kondekar, A new design approach of Dopingless tunnel FET for enhancement of device characteristics. IEEE Trans. Electron Devices 64(4), 1830–1836 (2017)ADSCrossRefGoogle Scholar
  15. 15.
    B.R. Raad, D. Sharma, P. Kondekar, K. Nigam, D.S. Yadav, Drain work function engineered doping-Less charge plasma TFET for ambipolar suppression and RF performance improvement: a proposal, design, and investigation. EEE Trans. Electron Devices 63(10), 3950–3957 (2016)ADSCrossRefGoogle Scholar
  16. 16.
    P. Ranade, H. Takeuchi, T.-J. King, C. Hu, Work function engineering of molybdenum gate electrodes by nitrogen implantation. Electrochem. Solid State Lett. 4(11), G85–G87 (2001)CrossRefGoogle Scholar
  17. 17.
    D. Wheeler, L.-E. Wernersson, L. Froberg, C. Thelander, A. Mikkelsen, K.-J. Weststrate, A. Sonnet, E.M. Vogel, A. Seabaugh, Deposition of HfO2 on InAs by atomic-layer deposition. Microelectronic. Eng. 86(86), 1561–1563 (2009)CrossRefGoogle Scholar
  18. 18.
    ATLAS Device Simulation Software, Silvaco Int (Santa Clara, California, USA, 2014)Google Scholar
  19. 19.
    F. Bashir, S.A. Loan, M. Rafat, A.R. Alamoud, S.A. Abbasi, A high performance gate engineered charge plasma based tunnel field effect transistor. J. Comput. Electron. 14(2), 477–485 (2015)CrossRefGoogle Scholar
  20. 20.
    Y. Yang, X. Tong, L.T. Yang, P.-F. Guo, L. Fan, Y.-C. Yeo, Tunneling field-effect transistor: capacitance components and modeling. IEEE Electron Device Lett. 31(7), 752–754 (2010)ADSCrossRefGoogle Scholar
  21. 21.
    J. Madan, R. Chaujar, Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans. Device Mater. Reliab. 16(2), 227–234 (2016)CrossRefGoogle Scholar
  22. 22.
    S.P. Kumar, A. Agrawal, R. Chaujar, R.S. Gupta, M. Gupta, Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor. Microelectron. Reliab. 51, 587–596 (2010)CrossRefGoogle Scholar
  23. 23.
    P. Ghosh, S. Haldar, R.S. Gupta, M. Gupta, An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design. IEEE Trans. Electron Devices 59(12), 3263–3268 (2012)ADSCrossRefGoogle Scholar
  24. 24.
    V. Saripalli, G. Sun, A. Mishra, Y. Xie, S. Datta, V. Narayanan, Exploiting heterogeneity for energy efficiency in chip multiprocessors. IEEE J. Emerg. Sel. Top. Circ. Syst. 1(2), 109–119 (2011)CrossRefGoogle Scholar
  25. 25.
    S. Ahish, D. Sharma, M.H. Vasantha, Y.B.N. Kumar, Device and circuit level performance analysis of novel InAs/Si heterojunction double gate tunnel field-effect transistor. Superlattices Microstruct. 94, 119–130 (2016)ADSCrossRefGoogle Scholar
  26. 26.
    Y.N. Chen, M.L. Fan, V.P.H. Hu, P. Su, C.T. Chuang, Design and analysis of robust tunneling FET SRAM. IEEE Trans. Electron Devices 60(3), 1092–1098 (2013)ADSCrossRefGoogle Scholar

Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2018

Authors and Affiliations

  1. 1.PDPM-Indian Institute of Information TechnologyDesign and ManufacturingJabalpurIndia

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