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Gate-tuned negative differential resistance observed at room temperature in an array of gold nanoparticles

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Abstract

We fabricated a single-electron (SE) device using gold nanoparticles (Au NPs). Drain, source, and gate electrodes on a SiO\({_2}\)/Si substrate were formed using electron beam lithography (EBL) and thermal evaporation of Au. Subsequently, solutions of 3-nm-diameter and 5-nm-diameter Au NPs were dropped on the device to make current paths through Au NPs among the electrodes. Measurements of the device exhibited negative differential resistance (NDR) in the current–voltage characteristics between the drain and source electrodes at room temperature (298 K). The NDR behavior was tuned by applying a gate voltage.

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Acknowledgements

This work was partly supported by JSPS KAKENHI Grant Number 15K13999 and by CREST, JST.

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Authors and Affiliations

  1. The University of Electro-Communications, Chofu, Tokyo, 182-8585, Japan

    Tran Thi Thu Huong, Kazuhiko Matsumoto, Masataka Moriya, Hiroshi Shimada & Yoshinao Mizugaki

  2. Tokyo University of Technology, Hachioji, Tokyo, 192-0982, Japan

    Yasuo Kimura

  3. Tohoku University, Sendai, Miyagi, 980-8579, Japan

    Ayumi Hirano-Iwata

Authors
  1. Tran Thi Thu Huong
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  2. Kazuhiko Matsumoto
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  3. Masataka Moriya
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  4. Hiroshi Shimada
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  5. Yasuo Kimura
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  6. Ayumi Hirano-Iwata
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  7. Yoshinao Mizugaki
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Correspondence to Tran Thi Thu Huong.

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Huong, T.T.T., Matsumoto, K., Moriya, M. et al. Gate-tuned negative differential resistance observed at room temperature in an array of gold nanoparticles. Appl. Phys. A 123, 268 (2017). https://doi.org/10.1007/s00339-017-0891-8

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