Adjustable passivation of SiO2 trap states in OFETs by an ultrathin CVD deposited polymer coating
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Trap state passivation at the interface of oxides with organic materials is crucial for the performance of electronic devices such as FETs or LEDs. Commonly used trap passivation layers such as octadecyltrichlorosilane or hexamethyldisilazane generate a highly hydrophobic surface, severely limiting the range of possible solvents for a subsequent layer deposition from solution. In this study, we investigate the trap passivation functionality of parylene C, known for its excellent encapsulation properties and chemical inertness. Parylene C coatings allow for a broad range of solvents to be used in the subsequent layer deposition. We observed a distinct gate bias stress effect in OFET devices due to a little, but constant seepage of charge through parylene C. The permeability of parylene C can be adjusted by thickness and thermal curing at moderate temperatures (100 °C).
KeywordsTrap State Gate Bias SiO2 Surface Electrical Stress Bias Stress
The authors acknowledge financial support via the MORPHEUS Project (FKZ: 13N11701-13N11706) of the Leading-Edge Cluster Forum Organic Electronics managed by InnovationLab GmbH within the High-Tech Strategy for Germany of the Federal Ministry of Education and Research.
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