Advertisement

Applied Physics A

, 122:988 | Cite as

Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

  • Rouzbeh Molaei Imen Abadi
  • Seyed Ali Sedigh Ziabari
Article

Abstract

In this paper, a first qualitative study on the performance characteristics of dual-work function gate junctionless TFET (DWG-JLTFET) on the basis of energy band profile modulation is investigated. A dual-work function gate technique is used in a JLTFET in order to create a downward band bending on the source side similar to PNPN structure. Compared with the single-work function gate junctionless TFET (SWG-JLTFET), the numerical simulation results demonstrated that the DWG-JLTFET simultaneously optimizes the ON-state current, the OFF-state leakage current, and the threshold voltage and also improves average subthreshold slope. It is illustrated that if appropriate work functions are selected for the gate materials on the source side and the drain side, the JLTFET exhibits a considerably improved performance. Furthermore, the optimization design of the tunnel gate length (L Tun) for the proposed DWG-JLTFET is studied. All the simulations are done in Silvaco TCAD for a channel length of 20 nm using the nonlocal band-to-band tunneling (BTBT) model.

Keywords

Work Function Subthreshold Slope Source Side Drain Side Tunnel Gate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    J.P. ColingeC, W. Lee, A. Afzalin, N.D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. Oneil, A. Blake, M. White, A.M. Kelleher, B. McCarthy, R. Murphy, Nanowire transistors without junctions. Nat. Nanotechnol. 5, 225–229 (2010)ADSCrossRefGoogle Scholar
  2. 2.
    S. GundapaneniM, R.K. Bajaj, K.V.R.M. Pandey, S.Ganguly Murali, A. Kottantharayil, Effect of band-to-band tunneling on junctionless transistors. IEEE Trans. Electron Devices 59(4), 1023–1029 (2012)ADSCrossRefGoogle Scholar
  3. 3.
    R. GandhiZ, N. Chen, K.Banerjee Singh, S. Lee, Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (≤50 mV/decade) at room temperature. IEEE Electron Device Lett. 32(4), 437–439 (2011)ADSCrossRefGoogle Scholar
  4. 4.
    A. Mallik, A. Chattopadhyay, The impact of fringing field on the device performance of a p-channel tunnel field-effect transistor with a high-κ gate dielectric. IEEE Trans. Electron Devices 59(2), 277–282 (2012)ADSCrossRefGoogle Scholar
  5. 5.
    R.S. Muller, T.I. Kamins, M. Chan, Device Electronics for Integrated Circuits (Wiley, New York, 2003), pp. 443–445Google Scholar
  6. 6.
    W.Y. ChoiB, G. Park, J.D. Lee, T.J.K. Lee, Tunneling field effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743–745 (2007)ADSCrossRefGoogle Scholar
  7. 7.
    A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energyefficient electronic switches. Nature 479(7373), 329–337 (2011)ADSCrossRefGoogle Scholar
  8. 8.
    R. Vishnoi, M.J. Kumar, Compact analytical model of dual material gate tunneling field effect transistor using interband tunneling and channel transport. IEEE Trans. Electron Devices 61(6), 1936–1942 (2014)ADSCrossRefGoogle Scholar
  9. 9.
    A.M. Ionescu, New functionality and ultralow power: key opportunities for post-CMOS era, in Proceedings of the International Symposium on VLSI Technology, Systems and Applcations, pp. 72–73, 2008Google Scholar
  10. 10.
    K.K. BhuwalkaS, A.K. Sedlmaier, C. Ludsteck, J.Schulze Tolksdorf, I. Eisele, Vertical tunnel field-effect transistor. IEEE Trans. Electron Devices 51(2), 279–282 (2004)ADSCrossRefGoogle Scholar
  11. 11.
    A.S. Verhulst, W.G. Vandenberghe, K. Maex, G. Groesenken, Tunnel field-effect transistor without gate-drain overlap. Appl. Phys. Lett. 91(5), 053102-1–053102-3 (2007)ADSCrossRefGoogle Scholar
  12. 12.
    S. Agarwal, G. Klimeck, M. Luisier, Leakage-reduction design concepts for low-power vertical tunneling field-effect ransistors. IEEE Electron Device Lett. 31(6), 621–623 (2010)ADSCrossRefGoogle Scholar
  13. 13.
    K.K. Bhuwalka, J. Schulze, I. Eisele, Scaling the vertical tunnel FET with tunnel bandgap modulation and gate work function engineering. IEEE Trans. Electron Devices 52(5), 909–917 (2005)ADSCrossRefGoogle Scholar
  14. 14.
    T. NirschlS, J. Henzler, M. Fischer, A.B. Flude, M. Stoffi, J. Sterkel, C. Sedlmeir, R. Weber, U. Heinrich, J. Schaper, R. Einfeld, U. Neubert, K. Feldmann, E. Stahrenberg, G. Rudere, A. Georgakos, R. Huber, W.Hansch Kakoschke, D.S. Lanssiedel, Scaling properties of the tunneling field effect transistor (TFET): device and circuit. Solid-State Electron. 50(1), 44–51 (2006)ADSCrossRefGoogle Scholar
  15. 15.
    S. Saurabh, M.J. Kumar, Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor. Jpn. J. Appl. Phys. 48(6), 064503 (2009)ADSCrossRefGoogle Scholar
  16. 16.
    E.H. Toh, G.H. Wang, G. Samudra, Y.C. Yeo, Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization. Appl. Phys. Lett. 90(26), 263507-1–263507-3 (2007)ADSCrossRefGoogle Scholar
  17. 17.
    O.M. NayfehC, N. Chleirigh, J. Hennessy, L. Gomez, J.L. Hoyt, D.A. Antoniadis, Design of tunneling field-effect transistors using strained-silicon/strained-germanium type-II staggered heterojunctions. IEEE Electron Device Lett. 29(9), 1074–1077 (2008)ADSCrossRefGoogle Scholar
  18. 18.
    J. AppenzellerY, M. Lin, J. Knoch, Z. Chen, P. Avouris, Comparing carbon nanotube transistors—the ideal choice: a novel tunneling device design. IEEE Trans. Electron Devices 52(12), 2568–2576 (2005)ADSCrossRefGoogle Scholar
  19. 19.
    A. Vandooren, R. Rooyackers, D. Leonelli, F. Iacopi, S.D. Gendt, A. Verhulst, M. Heyns, E. Kunnen, N.D. Nguyen, M. Demand, P. Ong, W. Lee, J. Moonens, O. Richards, W. Vandenberghe, G. Groeseneken, A 35 nm diameter vertical silicon nanowire short-gate tunnel FET with high-k/metal gate, in Proceedings of the IEEE Silicon Nanoelectronics Workshop, pp. 21–22, 2009Google Scholar
  20. 20.
    K. Boucart, W. Riess, A.M. Ionescu, Lateral strain profile as key technology booster for all-silicon tunnel FETs. IEEE Electron Device Lett. 30(6), 656–658 (2009)ADSCrossRefGoogle Scholar
  21. 21.
    C.-H. Shih, N.D. Chien, Sub-10-nm tunnel field-effect transistor with graded Si/Ge heterojunction. IEEE Electron Device Lett. 32(11), 1498–1500 (2011)ADSCrossRefGoogle Scholar
  22. 22.
    S. Saurabh, M.J. Kumar, Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans. Electron Devices 58(2), 404–410 (2011)ADSCrossRefGoogle Scholar
  23. 23.
    C. ShenS, L. Ong, C.H. Heng, G. Samudra, Y.C. Yeo, A variational approach to the two-dimensional nonlinear Poisson’s equation for the modeling of tunneling transistors. IEEE Electron Device Lett. 29(11), 1252–1255 (2008)ADSCrossRefGoogle Scholar
  24. 24.
    B. Ghosh, M.W. Akram, Junctionless tunnel field effect transistor. IEEE Electron. Device Lett. 34(5), 548–586 (2013)CrossRefGoogle Scholar
  25. 25.
    P.K. Asthana, B. Ghosh et al., High-speed and low power ultradeep-submicrometer III–V heterojunctionless tunnel field-effect transistor. IEEE Electron Device Lett. 61(2), 479–486 (2014)CrossRefGoogle Scholar
  26. 26.
    R.M.I. Abadiand, S.A.S. Ziabari, Representation of strained gate-all-around junctionless tunneling nanowire filed effect transistor for analog application. Microelectron. Eng. 162, 12–16 (2016)CrossRefGoogle Scholar
  27. 27.
    R.M.I. Abadiand, S.A.S. Ziabari, Representation of type I heterostructure junctionless tunnel field effect transistor for high-performance logic application. Appl. Phys. A 122, 616–623 (2016)ADSCrossRefGoogle Scholar
  28. 28.
    S.O. KoswattaS, J. Koester, W. Hanench, On the possibility of obtaining MOSFET-like performance and sub-60 mV/dec swing in 1-D broken gap tunnel transistors. IEEE Trans. Electron Devices 57(12), 3222–3486 (2010)ADSCrossRefGoogle Scholar
  29. 29.
    U. Khan, B. Ghosh, M.W. Akram, Effect of self-heating on selective buried oxide and silicon on insulator based junction less transistors. J. Low Power Electronics 9(3), 295–301 (2013)CrossRefGoogle Scholar
  30. 30.
    N. Cui, R. Liang, J. Xua, J. Xu, Heteromaterial gate tunnel field effect transistor with lateral energy band profile modulation. Appl. Phys. Lett. 2(2), 022111-1–022111-16 (2012)Google Scholar
  31. 31.
    G. LeeJ, S. Jang, W.Y. Choi, Dual-dielectric-constant spacer hetero-gate-dielectric tunneling field-effect transistors. Semicond. Sci. Technol. 28(5), 052001–052005 (2013)ADSCrossRefGoogle Scholar
  32. 32.
    M.J. Lee, W.Y. Choi, Effects of device geometry on hetero-gate-dielectric tunneling field-effect transistors. IEEE Electron Device Lett. 33(10), 1459–1461 (2012)ADSMathSciNetCrossRefGoogle Scholar
  33. 33.
    R.S. Saxena, M.J. Kumar, Dual material gate technique for enhanced transconductance and breakdown voltage of trench power MOSFETs. IEEE Trans. Electron Device 56(3), 517–522 (2009)ADSCrossRefGoogle Scholar
  34. 34.
    D.R. Lide, CRC Handbook on Chemistry and Physics, 89th edn. (Taylor & Francis, New York, 2008), pp. 12–114Google Scholar
  35. 35.
    W. Long, H. Ou, J.M. Kuo, K.K. Chin, Dual-material gate (DMG) field effect transistor. IEEE Trans. Electron Devices 46(5), 865–870 (1999)ADSCrossRefGoogle Scholar
  36. 36.
    K.Y. Na, Y.S. Kim, Silicon complementary metal-oxide semiconductor field-effect transistors with dual work function gate. Jpn. J. Appl. Phys. 45(12), 9033–9036 (2006)ADSCrossRefGoogle Scholar
  37. 37.
    C.H. Wangand, H. Chu, Y. S. Lai, Dual work-function metal gates. US Patent no. 73 81619B2, Jun 2008Google Scholar
  38. 38.
    ATLAS Users ManualSILVACO Int., Santa Clara, CA, 2009Google Scholar
  39. 39.
    K. Boucart, A.M. Ionescu, Double-gate tunnel FET with High-κ gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007)ADSCrossRefGoogle Scholar
  40. 40.
    A. Villalon, C.L. Royer, P. Nguyen, S. Barraud, F. Glowacki, A. Revelant, L. Selmi, S. Cristoloveanu, L. Tosti, C. Vizioz, J.M. Hartmann, N. Bernier, B. Previtali, C. Tabone, F. Allain, S. Martinie, O. Rozeau, M. Viner, First demonstration of strained SiGe nanowires TFETs with ION beyond 700 μA/μm, in Proceedings of the Symposium on VLSI Technology (VLSIT), Honolulu, HI, USA, pp. 66–67, 2014Google Scholar
  41. 41.
    W. HanschT, R.Kircher Vogelsang, M. Orlowski, Carrier transport near the Si/SiO2 interface of a MOSFET. Solid-State Electron. 32(10), 839–849 (1989)ADSCrossRefGoogle Scholar
  42. 42.
    A. Schenk, A model for the field and temperature dependence of SRH lifetimes in silicon. Solid State Electron. 35(11), 1585–1596 (1992)ADSCrossRefGoogle Scholar
  43. 43.
    P. Ranade, Y.C. Yeo, Q. Lu, Y.C. Yeo, H. Takeuch i, T.J. King, C. Hu, Molybdenum as a gate electrode for deep sub-micron CMOS technology, in Proceedings of the MRS Symposium, vol. 611, pp. C3.2.1–C3.2.6, 2000Google Scholar
  44. 44.
    I. Polishchuk, P. Ranade, T.J. King, C. Hu, Dual work function metal gate CMOS transistors by Ni–Ti interdiffusion. IEEE Electron Device Lett. 23(4), 200–202 (2002)ADSCrossRefGoogle Scholar
  45. 45.
    M. Hasan, H. Park, H. Yang, H. Hwang, H.S. Jung, J.H. Lee, Ultralow work function of scandium metal gate with tantalum nitride interface layer for n-channel metal oxide semiconductor application. Appl. Phys. Lett. 90(10), 103 510-1–103 510-3 (2007)CrossRefGoogle Scholar
  46. 46.
    V.V. NagavarapuR, R. Jhaveri, J.C.S. Woo, The tunnel source (PNPN) n-MOSFET: a novel high performance transistor. IEEE Trans. Electron Devices 55(4), 1013–1019 (2008)ADSCrossRefGoogle Scholar
  47. 47.
    A. Tura, Z. Zhang, P. Liu, Y.H. Xie, J.C. Woo, Vertical silicon p–n–p–n tunnel nMOSFET with MBE-grown tunneling junction. IEEE Trans. Electron Devices 58(7), 1907–1913 (2011)ADSCrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2016

Authors and Affiliations

  • Rouzbeh Molaei Imen Abadi
    • 1
  • Seyed Ali Sedigh Ziabari
    • 1
  1. 1.Department of Electrical EngineeringRasht BranchIslamic Azad UniversityRashtIran

Personalised recommendations