Skip to main content

Efficient controller synthesis for a fragment of \(\hbox {MTL}_{0, \infty }\)

Abstract

In this paper we offer an efficient controller synthesis algorithm for assume-guarantee specifications of the form \(\varphi _1 \wedge \varphi _2 \wedge \cdots \wedge \varphi _n \rightarrow \psi _1 \wedge \psi _2 \wedge \cdots \wedge \psi _m\). Here, \(\{\varphi _i,\psi _j\}\) are all safety-MTL\(_{0, \infty }\) properties, where the sub-formulas \(\{\varphi _i\}\) are supposed to specify assumptions of the environment and the sub-formulas \(\{\psi _j\}\) are specifying requirements to be guaranteed by the controller. Our synthesis method exploits the engine of Uppaal-Tiga and the novel translation of safety- and co-safety-MTL\(_{0, \infty }\) properties into under-approximating, deterministic timed automata. Our approach avoids determinization of Büchi automata, which is the main obstacle for the practical applicability of controller synthesis for linear-time specifications. The experiments demonstrate that the chosen specification formalism is expressive enough to specify complex behaviors. The proposed approach is sound but not complete. However, it successfully produced solutions for all the experiments. Additionally we compared our tool with Acacia+ and Unbeast, state-of-the-art LTL synthesis tools; and our tool demonstrated better timing results, when we applied both tools to the analogous specifications.

This is a preview of subscription content, access via your institution.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5

Notes

  1. 1.

    For instance, there is no equivalent deterministic Timed Automata for MTL\(_{0,\infty }\) property \(\Diamond _{\le 1}(p \wedge \Box _{\le 1}(\lnot r) \wedge \Diamond _{\le 1}(q))\). This can be proved by adapting the proof of [25] that MITL\(_{[a,b]}\) formula \(\Box _{\le 1}(p \rightarrow \Diamond _{[1,2]}(\lnot q))\) is not determinizable.

  2. 2.

    As we will define in Sect. 2, \(\widehat{\Box }\) and \(\widehat{\mathrm{U}}\) are modifications of the “classical” globally and until operators that do not take into account the first observation of a trace.

References

  1. 1.

    Alur, R: Formal verification of hybrid systems. In: Proceedings of the  Ninth ACM International Conference on Embedded Software (EMSOFT ’11), pap. 273–278. ACM, New York, NY, USA (2011)

  2. 2.

    Alur, R., Dill, D.L.: A theory of timed automata. Theor. Comput. Sci. 126, 183–235 (1994)

    Article  MATH  MathSciNet  Google Scholar 

  3. 3.

    Alur, R., Feder, T., Henzinger, T.A.: The benefits of relaxing punctuality. J. ACM 43(1), 116–146 (1996)

    Article  MATH  MathSciNet  Google Scholar 

  4. 4.

    Babiak, T., Kretínský, M., Rehák, V., Strejcek, J.: LTL to Büchi Automata Translation: Fast and More Deterministic. CoRR, abs/1201.0682 (2012)

  5. 5.

    Behrmann, G., Cougnard, A., David, A., Fleury, E., Larsen, K.G., Lime, D.: Uppaal-tiga: time for playing games! In: Proceedings of the 19th International Conference on Computer Aided Verification, Number 4590 in LNCS, pp. 121–125. Springer, Berlin (2007)

  6. 6.

    Behrmann, G., David, Re, Larsen, K.G.: A Tutorial on Uppaal. Springer, Berlin (2004)

    Google Scholar 

  7. 7.

    Bloem, R., Galler, S., Jobstmann, B., Piterman, N., Pnueli, A., Weiglhofer, M.: Specify, compile, run: hardware from PSL. In: 6th International Workshop on Compiler Optimization Meets Compiler Verification (2007)

  8. 8.

    Bloem, R., Jobstmann, B., Piterman, N., Pnueli, A., Sa’ar, Y.: Synthesis of reactive(1) designs. J. Comput. Syst. Sci. 78(3), 911–938 (2012)

    Article  MATH  MathSciNet  Google Scholar 

  9. 9.

    Bohy, A., Bruyère, V., Filiot, E., Jin, N., Raskin, J.-F.: Acacia+, a tool for LTL synthesis. In: Proceedings of the 24th International Conference on Computer Aided Verification, CAV’12, pp. 652–657. Springer, Berlin, Heidelberg (2012)

  10. 10.

    Bouyer, P., Bozzelli, L., Chevalier, F.: Controller synthesis for MTL specifications. In: Proceedings of the 17th International Conference on Concurrency Theory (CONCUR’06) (2006)

  11. 11.

    Buchi, J.R., Landweber, L.H.: Solving sequential conditions by finite-state strategies. Trans. Am. Math. Soc. 138, 295–311 (1969)

    Article  MathSciNet  Google Scholar 

  12. 12.

    Bulychev, P., David, A., Larsen, K. G., Legay, A., Li, G., Poulsen, D. B., Stainer, A.: Monitor-based statistical model checking for weighted metric temporal logic. In: LPAR (2012)

  13. 13.

    Cassez, F., David, A., Fleury, E., Larsen, K. G., Lime, D.: Efficient on-the-fly algorithms for the analysis of timed games. In: CONCUR’05, volume 3653 of LNCS, pp. 66–80. Springer, Berlin (August 2005)

  14. 14.

    Church, A.: Logic, Arithmetic. Automata. In: Proceedings of the International Mathematical Congress (1962)

  15. 15.

    David, A., Behrmann, G., Bulychev, P., Byg, J., Chatain, T., Larsen, T.G., Pettersson, P., Rasmussen, J., Srba, J., Yi, W., Joergensen, K.Y., Lime, D., Magnin, M., Roux, O.H., Traonouez, L.-M.: Tools for model-checking timed systems. In: Roux O.H., Claude, J. (eds.) Communicating Embedded Systems—Software and Design, pp. 165–225. ISTE Publishing, Wiley, New York (2009)

  16. 16.

    Di Giampaolo, B., Geeraerts, G, Raskin, J.F., Sznajder, N.: Safraless procedures for timed specifications. In: Springer (ed.) Proceedings of FORMATS 2010, 8th International Conference on Formal Modelling and Analysis of Timed Systems, volume 6246 of, Lecture Notes in Computer Science, pp. 2–22, (2010)

  17. 17.

    Doyen, L., Geeraerts, G., Raskin, J.F., Reicher, J.: Realizability of real-time logics. In: Proceedings of FORMATS 2009, 7th International Conference on Formal Modeling and Analysis of Timed Systems, volume 5813 of Lecture Notes in Computer Science, pp. 133–148. Springer, Berlin (2009)

  18. 18.

    Ehlers, R.: Symbolic bounded synthesis. In: Touili, T., Cook, B., Jackson, P. (ed.) 22nd International Conference on Computer Aided Verification, volume 6174 of LNCS, pp. 365–379. Springer, Berlin (2010)

  19. 19.

    Emerson, E.A., Clarke, E.M.: Using branching time temporal logic to synthesize synchronization skeletons. Sci. Comput. Program. 2(3), 241–266 (1982)

    Article  MATH  Google Scholar 

  20. 20.

    Filiot, E., Jin, N., Raskin, J.-F.: An antichain algorithm for LTL realizability. In: CAV, pp. 263–277 (2009)

  21. 21.

    Filiot, E., Jin, N., Raskin, J.-F.: Exploiting structure in LTL synthesis. Int. J. Softw. Tools Technol. Transf. (STTT) 541–561 (2013). doi:10.1007/s10009-012-0222-5

  22. 22.

    Gómez, R., Bowman, H.: Efficient detection of zeno runs in timed automata. In: Proceedings of the 5th International Conference on Formal Modeling and Analysis of Timed Systems, FORMATS’07, pp. 195–210. Springer, Berlin, Heidelberg (2007)

  23. 23.

    Kupferman, O., Piterman, N., Vardi, M.Y.: Safraless compositional synthesis. In: 18th Conference on Computer Aided Verification, pp. 31–44 (2006)

  24. 24.

    Kupferman, O., Vardi, M.Y.: \(\mu \)-Calculus synthesis. In: MFCS, pp. 497–507 (2000)

  25. 25.

    Maler, O., Nickovic, D., Pnueli, A.: Real time temporal logic: past, present, future. In: FORMATS, pp. 2–16 (2005)

  26. 26.

    Maler, O., Nickovic, D., Pnueli, A.: On synthesizing controllers from bounded-response properties. In: CAV, pp. 95–107 (2007)

  27. 27.

    Maler, O., Pnueli, A., Sifakis, J.: On the synthesis of discrete controllers for timed systems. In: Mayr, E.W., Puech, C. (eds.) Proceedings of the STACS’95, LNCS 900, pp. 229–242. Springer, Berlin (1995)

  28. 28.

    Manna, Z., Wolper, P.: Synthesis of communicating processes from temporal logic specifications. ACM Trans. Program. Lang. Syst. 6(1), 68–93 (1984)

    Article  MATH  Google Scholar 

  29. 29.

    Ouaknine, J., Worrell, J.: On the decidability of metric temporal logic. In: Proceedings of the 20th Annual IEEE Symposium on Logic in Computer Science, LICS ’05, pp. 188–197. IEEE Computer Society, Washington, DC, USA (2005)

  30. 30.

    Piterman, N., Pnueli, A., Sa’ar, Y.: Synthesis of reactive(1) designs. In: Proceedings of the Verification, Model Checking, and Abstract Interpretation (VMCAI 06), pp. 364–380. Springer, Berlin (2006)

  31. 31.

    Pnueli, A., Rosner, R.: On the synthesis of a reactive module. In: Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on principles of programming languages (POPL ’89), pp. 179–190. ACM, New York, NY, USA (1989)

  32. 32.

    Ramadge, P., Wonham, W.: Supervisory control of a class of discrete event processes. SIAM J. Control Optim. 25(1), 206–230 (1987)

    Article  MATH  MathSciNet  Google Scholar 

  33. 33.

    Schewe, S., Finkbeiner, B.: Bounded synthesis. In: ATVA, volume 4762 of Lecture Notes in Computer Science, pp. 474–488. Springer, Berlin (2007)

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to Peter Bulychev.

Additional information

The research leading to these results has received funding from the European Union Seventh Framework Programme (FP7/2007-2013) under grant agreement n 601148 (Cassting). This publication reflects only the authors views and the Union is not liable for any use that may be made of the information contained herein. Also, the paper is supported by the Danish National Research Foundation, the National Natural Science Foundation of China (Grant No. 61061130541) for the Danish-Chinese Center for Cyber Physical Systems and VKR Center of Excellence MT-LAB.

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Bulychev, P., David, A., Larsen, K.G. et al. Efficient controller synthesis for a fragment of \(\hbox {MTL}_{0, \infty }\) . Acta Informatica 51, 165–192 (2014). https://doi.org/10.1007/s00236-013-0189-z

Download citation