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Analysis and experimental tests of a solid-state fault current limiter

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Abstract

The increase in distribution power demand and distributed generation may lead to a rise in power substation fault current levels. One possible solution to this problem is the use of a solid-state fault current limiter (SS-FCL). In this context, this paper proposes the concept of a bridge-type solid-state device switching an air-core reactor as an SS-FCL topology. The overvoltage protection system details are presented, along with an explanation of the fault detection algorithm control's principle. An experimental setup is designed to evaluate various events in addition to the short-circuit, such as load-steps, harmonic loads, motor startups, and transformer’s inrush. Fault current is detected within one millisecond, with a total reduction of 42%. The overvoltage protection system clamped the peak voltage across the semiconductor switch and kept the dV/dt below the maximum stipulated. The load input tests showed a proper limiting operation and provided that the device is within the parameterization range.

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Acknowledgements

The authors would like to thank Light Serviços de Eletricidade S/A by granting the ANEEL 133/20 R and D project entitled "Development of a Medium Voltage Prototype Fault Current Limiter for Distribution Systems." This study was financed in part by the Brazilian Federal Agency for Support and Evaluation of Graduate Education (Coordenação de Aperfeiçoamento de Pessoal de Nível Superior—Brasil, CAPES)—Finance Code 001. The authors would also like to thank the National Council for Scientific and Technological Development (Conselho Nacional de Desenvolvimento Científico e Tecnológico, CNPq), the National Institute of Science and Technology in Electricity (Instituto Nacional de Ciência e Tecnologia em Energia Elétrica, INCT-Inerge), the Rio de Janeiro Research Support Foundation (Fundação de Amparo à Pesquisa do Estado do Rio de Janeiro, FAPERJ), and Centro Integrado de Tradução e Escrita (CITE/UFF) for assistance with English language translation and developmental editing.

Funding

This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior—Brasil (CAPES)—Finance Code 001, and an ANEEL 133/20 R and D project entitled "Development of a Medium Voltage Prototype Fault Current Limiter for Distribution Systems."

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Authors and Affiliations

  1. Universidade Federal Fluminense, Niterói, RJ, Brazil

    Alexandre Bitencourt, Cauê Nogueira, Gabriel dos Santos, D. H. N. Dias, B. W. França, F. Sass & G. G. Sotelo

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  1. Alexandre Bitencourt
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  2. Cauê Nogueira
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  3. Gabriel dos Santos
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  4. D. H. N. Dias
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  5. B. W. França
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  6. F. Sass
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  7. G. G. Sotelo
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Contributions

AB helped in conceptualization, investigation, methodology, writing—original draft, writing—review and editing, data curation, visualization, and formal analysis; CN helped in conceptualization, investigation, and methodology; GS helped in conceptualization, investigation, and methodology; DD worked in supervision, validation, and funding acquisition; BF worked in supervision, validation, and funding acquisition; FS worked in supervision, validation, and funding acquisition; and GS worked in supervision, validation, and funding acquisition.

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Correspondence to Alexandre Bitencourt.

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Bitencourt, A., Nogueira, C., dos Santos, G. et al. Analysis and experimental tests of a solid-state fault current limiter. Electr Eng 105, 3219–3228 (2023). https://doi.org/10.1007/s00202-023-01880-w

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  • DOI: https://doi.org/10.1007/s00202-023-01880-w

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