# Handling input voltage frequency variations in power factor correctors with pre-calculated duty cycles

## Abstract

The use of pre-calculated duty cycles for power factor correction leads to a significant simplification of the design and a reduction of the final cost. There are previous proposals for handling non-nominal conditions such as input voltage or load variations in pre-calculated power factor correction. However, there are no proposals for handling input frequency variations for this kind of pre-calculated duty cycles controllers, which have an important impact in the power factor even if they are small variations. This paper measures this impact and includes two alternative solutions to handle the variations of the input frequency. The results show that the introduction of either of these solutions keeps the power factor values over 0.991 and the input current total harmonic distortion below 11.33% for an input frequency range from 48 to 52 Hz.

## Keywords

Power factor correction Field programmable gate arrays Frequency robustness## 1 Introduction

The initial approach to power factor correction (PFC) implies sensing both the input and output voltages and the input current. Analog control proposals have provided cheap and functional solutions for many years. However, the lowering of prices of digital devices and their ease of use have increased their application for PFC. Digital solutions rely on different type of devices for this task. Literature shows examples of the utilization of microcontrollers, digital signal processors [1, 2, 3, 4] and Field Programmable Gate Arrays (FPGAs) [5, 6] for solving PFC.

Although digital devices have demonstrated enough capability for dynamically calculating the actuation in real time [7], these solutions require several analog to digital converters (ADCs), increasing the cost of the digital solution. To reduce costs and to simplify the design of the controller, several works estimate the input current. Literature presents the estimation of the input current by using the voltage ADC measurements in dc–dc multiphase converters [8, 9, 10]. For PFC the use of input and output voltage ADCs allows the estimation of the input current [11, 12]. It is also possible to avoid the use of ADCs using external voltage comparators [13]. When DCM or the boundary of CCM and DCM is used, only the zero-crossing detection of the current is necessary. Literature also presents examples of avoidance of resistors or transformers to detect the zero-crossing of the inductor current by means of an auxiliary circuit [14]. However, for converters operating in CCM, there are also proposals of current sensor avoidance. This reduction of the number of sensors usually goes with a reduction in the number of loops. In [15] PFC is achieved implementing only an output voltage loop, which obtains high power factor (PF) in nominal conditions. This technique, known as single-loop current sensorless control (SLCSC), uses a pre-stored sine function phase shifted an angle proportional to the output of the voltage loop. Therefore, the synchronization with the AC-mains is critical, which is achieved using a PLL as explained in [16], in which the SLCSC technique is explored in further detail. An evolution of the SLCSC technique for improved PF under distorted input voltage is presented in [17], but in that case the input voltage must be measured all the time with an ADC instead of just its synchronization through a PLL as in [15, 16]. In [18] an adaptive nonlinear observer estimates the load value without using a current sensor.

Main characteristics of different existing proposals for PFC

[17] | [13] | [14] | [18] | [21] | |||||
---|---|---|---|---|---|---|---|---|---|

Without sensing input voltage | Partial | No | No | Yes | No | No | Partial | Partial | Partial |

Without sensing current | Yes | Yes | Yes | No | Yes | Yes | Yes | Yes | Yes |

Without sensing output voltage | No | No | No | No | No | No | No | No | No |

Fixed switching frequency | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |

Utility frequency variation tolerant | No | Yes | Yes | Yes | Yes | Yes | No | No | No |

Previous works focused on handling variations in the load or input voltage amplitude while preserving the PF. This work focuses on the performance of a pre-calculated system when the frequency of the input voltage differs from the nominal value. The standard EN50160 [25] describes the low-voltage supply characteristics for Europe. The power frequency for interconnected supply systems is 50 Hz \(\pm 1\%\) during 99.5% of a year and a frequency of 50 Hz + 4% / −6% during 100% of the time. An equivalent phenomenon is observed due to frequency inaccuracies of the clock of the digital controller device. This inaccuracy leads to the application of the pre-calculated values in a different moment as they were intended to be applied. Although these frequency changes are small, they have an important impact in the obtained PF using pre-calculated or SLCSC techniques. On one hand, closed loop control methods that continuously measure and use the value of the input voltage are inherently immune to this kind of frequency variation. On the other hand, every control method that relies on the use of pre-calculated data (either duty cycles [19, 20, 21, 22, 23] or sine values [15, 16]) and synchronizes with the AC-mains using the zero-crossing event are sensible to these frequency variations. The impact of a frequency deviation within standard’s limits shows that a pre-calculated method generates a THD over 40% and a relevant decrease in the obtained PF. A 4% frequency variation decreases the PF value to 0.710 when using a pre-calculated controller. Therefore, every control method that relies on pre-calculated data should include an AC-mains frequency adaptation module to fulfill standard commercial requirements. The proposal technique is presented using pre-calculated duty cycles, but it could be adapted to SLCSC changing the memory of pre-calculated duty cycles by the memory of sine values used in SLCSC.

This paper is organized as follows. Section 2 describes the modifications made to a pre-calculated duty cycle controller to handle frequency variations. Section 3 presents theoretical analysis of these modifications. Section 4 shows the experiments performed with the new implementation. Section 5 presents a discussion about the obtained results. Finally, Section 6 summarizes this work.

## 2 Development

Precalculated PFC systems are very sensitive to variations of the real conditions versus the nominal ones. These variations comprise variations in load or input voltage, including variations in the input voltage frequency. In fact, standards such as EN50160 define the maximum possible frequency variation. The same effect is produced by the inaccuracies in the digital clock of the controller, used for determining the current instant in the input voltage period. Or even asymmetries in the input AC voltage also lead to the same effect: inaccuracies between the instant where the pre-calculated cycles are applied and when they were supposed to be applied.

This work describes the modifications required to a pre-calculated controller to handle non-nominal frequency conditions. Particularly, the development and experiments have been applied to a three duty cycle component controller, as three is the maximum number of different components in the duty cycle found in the literature for pre-calculated PFC systems [23]. However, the same modifications are valid for any pre-calculated controller.

The design of a pre-calculated controller requires defining the switching frequency (i.e., the number of PWM periods for each AC-mains half cycle) and the resolution of the PWM. These will define the minimum required clock frequency of the final device. In this work, an AC-mains frequency of 50 Hz and a switching frequency of 100 kHz are imposed by the power design stage, so there are 1000 switching cycles inside an AC half cycle. The achieved PWM resolution can be inferred dividing the clock frequency by the switching frequency. In this paper, a clock frequency of 100 MHz is used (in this case imposed by the FPGA used for the control), so there are 1000 possible duty cycle values in a switching cycle. Taking this PWM resolution, every duty cycle needs 10 bits in order to store its value inside the block RAM. In order to improve the PWM resolution, 5 additional bits are used following a dither approach [26]. Therefore, every duty cycle is finally generated using 15 bits. Using this information and the nominal working conditions (see Sect. 3), the values of each duty cycle (*D*(*k*)), or its components, can be calculated and stored (e.g., in a RAM block memory).

The proposal of this paper is to include a frequency loop to modify the number of pre-calculated duty cycles applied in each utility period. This frequency loop measures the time between consecutive restart pulses to obtain the duration of every AC-mains half cycle. However, only the duration of the last two half cycles is stored. This allows the controller to be configured to use both or to segregate the positive half cycles from the negative ones, to handle possible AC asymmetries.

The pre-calculated controller can adapt to the measured AC-mains half cycle frequency by means of modifying the \(f_{SW}\) or by modifying the number of fixed-frequency PWM cycles applied. The adaptation of the \(f_{SW}\) requires using a variable-frequency PWM module and a multiplier to adapt the values of the pre-calculated duty cycle vector. The modification of the number of fixed-frequency PWM cycles uses the difference between the measurement and the nominal value to define the number of PWM cycles that must be removed (for higher frequencies) or inserted (for lower frequencies). The absolute value of this difference is in the range [0, 60] PWM cycles, corresponding to the variation of a 6% of the frequency and 1000 PWM cycles per AC-mains half cycle.

Both fixed and variable switching frequency have advantages and disadvantages. Fixed switching frequency is usually preferred for higher power applications [27] and in some cases it is a design requirement, so this paper focuses on the fixed-frequency solution. However, a solution using a slightly variable switching frequency, proportional to the input voltage frequency, would be possible and very similar in terms of hardware resources, using a multiplier to adapt the on-time depending on the measured frequency. This paper proposes the dynamic generation of the new duty cycle vector using the original one by means of two different approaches: skipping or repeating the existing values or recalculating a new vector by means of interpolation. These techniques are similar either if the controller stores the final duty cycle values or their sub-components. Each approach will be explained in the next sections.

### 2.1 The skip-repeat approach

The skip-repeat approach defines the new sequence of PWM duty cycles (\(D^{skip-rep.}(k)\)) by means of skips or repetitions of equally distributed duty cycles of the original sequence of 1000 values. For this task, the new module uses a 61-position LUT which stores, for each absolute value of the difference, the index of the first PWM cycle to be skipped/repeated (9 bits). The complete list of PWM cycles indexes to be skipped/repeated is dynamically calculated adding the stored value to the last index until there are as many indexes as needed. Considering the situation of an AC-mains 0.2% faster of its nominal value, the half cycle would only last 998 PWM cycles. The controller would require to skip two duty cycles from the original 1000 vector. In this circumstance, the values at the indexes 333 and 666 would be skipped.

When the frequency of the input voltage is higher than the nominal value, the module must remove PWM cycles. Therefore, the frequency regulation module will skip the PWM duty cycle corresponding to the ones included in the list of indexes presented before. Otherwise, when the frequency of the input voltage is lower than the nominal value, the module must insert new PWM duty cycles. These new duty cycles are repetitions of those values with the index included in the list.

Following the previous example, the situation when the measured frequency is 0.2% faster, the half cycle will last 998 PWM cycles, being the difference of the measured number of PWM cycles minus the nominal value: \(`-2'\). The aforementioned LUT stores for the value ‘2’, as only the absolute difference is considered, the value ‘333’. This value is the index of the first duty cycle in which an action has to be performed. The module considers the sign of the difference to decide if the duty ‘333’ has to be repeated (positive sign) or skipped (negative sign). Similarly, a 0.2% slower measured AC frequency will require 1002 PWM cycles per half cycle. In this case, the information from the LUT also retrieves the value ‘333’ as the first index to require an action. In this case, the positive sign of the difference will make the controller to repeat the duty cycle at this index. For both cases, the second index to require an action is ‘666’. The frequency module calculates the list of the indexes to include all required modifications and compensates the integer rounding applied to the index list generation.

### 2.2 The interpolation approach

Following the previous examples, considering the situation when the measured frequency is 0.2% higher, the AC half cycle will last 998 PWM cycles, being the difference of the measured number of PWM cycles minus the nominal value ‘\(-2\)’. The aforementioned LUT stores for the value ‘\(-2\)’ the increment 1.002. The first duty cycle to be applied is the pre-calculated duty cycle stored at position 0 (\(D^{inter.}(0) = D(0)\)). The second one (\(D^{inter.}(1)\)) would be the one stored at position 1.002, meaning that the duty cycle value has to be interpolated as \( D^{inter.}(1) = 0.998 \cdot D(1) + 0.002 \cdot D(2)\). The third one (\( D^{inter.}(2)\)) would be \(1.002 \cdot 2 = 2.004\), which has also to be interpolated using \(D^{inter.}(2) = 0.996 \cdot D(2) + 0.004 \cdot D(3)\). By the time the next zero-crossing instant occurs, the controller would have applied 998 duty cycles correctly distributed. In a similar way, a 0.2% slower AC-mains frequency will require 1002 PWM cycles per semi cycle. In this situation, the LUT stores for the value ‘2’ the increment 0.998. Like before, the first duty cycle to be applied is the one stored at position 0 (\(D^{inter.}(0) = D(0)\)). The second one (\(D^{inter.}(1)\)) would be the one stored at position 0.998, meaning that the duty cycle value has to be interpolated as \( D^{inter.}(1) = 0.002 \cdot \)D(0)\( + 0.998 \cdot D(1)\). By the time the next zero-crossing instant occurs, the controller would have applied 1002 duty cycles correctly distributed. The examples of these two approaches have been depicted in Fig. 3.

A modification to the original controller is required replacing the original RAM block by a dual-port RAM, which allows simultaneous access to two different stored values. The retrieved duty cycles are interpolated using the corresponding weights obtaining a new duty cycle. As depicted in Fig. 4, this solution is not as transparent as the skip-repeat approach. It not only requires a different RAM block, but also requires two new multipliers and an adder to solve the problem.

The resources required by each of the proposed systems are presented in Table 2. The skip-repeat approach increases the number of FFs and the 4-input LUTs as it requires to store the index LUT. The interpolation approach shows a small increase of FFs and LUTs over the skip-repeat approach. However, the main drawback of this approach is the increase of multipliers.

Although both proposed solutions (the skip-repeat and the interpolation ones) imply additional resources, these are negligible compared to the necessary resources for storing a complete set of duty cycles for each possible frequency which would be a brute force approximation to the problem of frequency variations: storing a different set of duty cycles for each frequency. This direct approach, in the case of a three component-based duty calculation, would require \(121 \cdot 3 = 363\) RAMB16 blocks (a RAMB16 block is a RAM memory of 16 kbits), which would require a more complex and expensive device than the one required for implementing the proposed approach.

## 3 Numerical analisys

The different approaches have been numerically analyzed to measure their impact on a PFC boost converter. The first analysis focuses on the error of the duty cycle and the second one focuses on the impact on the input current. These two analysis have been generated for the cases of an input frequency of 49 and 51 Hz.

### 3.1 Error in the duty cycle

Synthesis requirements for each of the alternative designs

System | FFs | 4-Input LUTs | MULT 18X18 | RAMB16 modules |
---|---|---|---|---|

Original pre-calculated PFC controller | 650 | 1396 | 6 | 3 |

Skip-repeat freq. loop | 1076 | 3042 | 6 | 3 |

Interpolation freq. loop | 1124 | 3090 | 12 | 3 |

Observing Figs. 5 and 6, it is important to notice that the duty cycle error around the middle of the AC-mains half cycle is near zero. As the input voltage reaches its maximum values during this part of the AC-mains, the duty cycle error of this part has more impact on the final result, decreasing the PF distortion.

### 3.2 Impact on the input current

*k*is obtained from (3).

*D*(

*k*), it uses the corresponding one generated by each algorithm (\(D^{skip-rep.}(k)\) or \(D^{inter.}(k)\)). Using this ideal input current, (4) defines the input current error for the skip-repeat approach and (5) establishes the interpolation approach.

Duty error histogram obtained using the skip-repeat and the interpolated approaches at 49 and 51 Hz

Duty error | 49 Hz | 51 Hz | ||
---|---|---|---|---|

Skip-Rep. | Int. | Skip-Re. | Int. | |

\(-\)0.003 | 0 | 0 | 1 | 0 |

\(-\)0.002 | 0 | 6 | 45 | 0 |

\(-\)0.001 | 109 | 253 | 240 | 55 |

0 | 504 | 359 | 549 | 648 |

0.001 | 8 | 6 | 2 | 2 |

0.002 | 310 | 358 | 141 | 271 |

0.003 | 88 | 37 | 2 | 3 |

0.004 | 1 | 0 | 0 | 0 |

0.005 | 0 | 1 | 0 | 1 |

Whereas Fig. 7 presents the ideal input current and the representation of \(e^{inter.}_{i}(k)\) and \(e^{skip-rep.}_{i}(k)\) when the input frequency is 49 Hz, Fig. 8 shows the same results for a frequency of 51 Hz. It is possible to conclude that the current error when applying any of the proposed methods is relatively small (less than 13% in the worst case), so the proposed methods are theoretically feasible.

## 4 Experiments

The experiments have been carried out over a boost converter (\(L = 5~mH, C = 68~\upmu F\), P = 300 W, \(V_{g-eff}\) = 230 V, \(V_\mathrm{out}\) = 400 V, \(f_{SW} = 100\) kHz). The controller has been implemented using an FPGA Xilinx XC3S1000-4FT256. The clock frequency of the system is 100 MHz. The utility period has been divided into 1000 PWM cycles. For each of these cycles, the PWM may be set to a duty cycle from 0 to 999. The three components of the 1000 duty cycles have been pre-calculated offline and stored in the FPGA.

Power factor and THD values for the different input voltage frequencies (nominal, \(\pm 1\) and \(\pm 2\) Hz) and the different proposed controlling methods

PF | Frequency (Hz) | |||||
---|---|---|---|---|---|---|

48 | 49 | 50 | 51 | 52 | ||

a | Precalculated PFC controller without freq. loop | 0.710 | 0.888 | 0.979 | 0.949 | 0.864 |

b | Skip-repeat freq. loop using last measure | 0.935 | 0.933 | 0.930 | 0.928 | 0.927 |

c | Skip-repeat freq. loop using last equivalent measure | 0.994 | 0.993 | 0.992 | 0.991 | 0.991 |

d | Skip-repeat freq. loop using average of last two measures | 0.982 | 0.980 | 0.977 | 0.973 | 0.975 |

e | Interpolation freq. loop using last measure | 0.936 | 0.933 | 0.931 | 0.935 | 0.931 |

f | Interpolation freq. loop using last equivalent measure | 0.994 | 0.993 | 0.993 | 0.992 | 0.992 |

g | Interpolation freq. loop using average of last two measures | 0.981 | 0.980 | 0.977 | 0.976 | 0.977 |

h | Specifically calculated duty cycle vectors (base line) | 0.994 | 0.994 | 0.993 | 0.993 | 0.993 |

Iin THD (%) | Frequency (Hz) | |||||
---|---|---|---|---|---|---|

48 | 49 | 50 | 51 | 52 | ||

a | Original pre-calculated PFC controller | 43.31 | 27.43 | 17.70 | 21.93 | 35.80 |

b | Skip-repeat freq. loop using last measure | 25.72 | 25.73 | 26.28 | 27.00 | 26.99 |

c | Skip-repeat freq. loop using last equivalent measure | 9.22 | 9.34 | 10.22 | 10.57 | 11.33 |

d | Skip-repeat freq. loop using average of last two measures | 16.99 | 17.99 | 18.11 | 18.72 | 18.25 |

e | Interpolation freq. loop using last measure | 25.86 | 25.86 | 26.39 | 26.06 | 26.86 |

f | Interpolation freq. loop using last equivalent measure | 9.45 | 9.87 | 10.15 | 10.81 | 11.22 |

g | Interpolation freq. loop using average of last two measures | 16.72 | 17.22 | 17.96 | 18.37 | 18.50 |

h | Specifically calculated duty cycle vectors (base line) | 9.86 | 10.05 | 10.02 | 10.06 | 10.42 |

The power source used in the experiments is a Pacific Power Source 115-ASX. This power source allows the modification of the AC frequency provided to the boost converter. To obtain the measures the Tektronix PA1000 Power Analyzer has been used.

- a.
The pre-calculated regulator without frequency loop, which applies a pre-calculated duty cycle controller without any frequency correction.

- b.
The skip-repeat frequency loop modifying the duty cycle vector considering no discrimination between positive and negative half cycles.

- c.
The skip-repeat frequency loop modifying the duty cycle vector considering the frequency measured in the last equivalent half cycle (positive or negative).

- d.
The skip-repeat frequency loop modifying the duty cycle vector considering the average of the measurements of the last two half cycles.

- e.
The interpolating frequency loop modifying the duty cycle vector considering the frequency measured in the last half cycle, with no discrimination between positive and negative half cycles.

- f.
The interpolating frequency loop modifying the duty cycle vector considering the frequency measured in the last equivalent half cycle (positive or negative).

- g.
The interpolating frequency loop modifying the duty cycle vector considering the average of the measurements of the last two half cycles.

- h.
The base line value using specifically calculated duty cycles for each AC half cycle at each frequency.

## 5 Discussion

Figure 9 shows the input current (green at the top), the rectified input voltage (red in the middle) and the duration of each half cycle (orange at the bottom) waveforms for different systems and frequencies. The left column shows the results for 48 Hz, the central column for 50 Hz and the right column for 52 Hz. The analysis is done taking into account Table 4 and Fig. 9.

The first point of discussion is related to the results obtained from the different systems in nominal conditions (50 Hz). The original method, the pre-calculated controller (option a)), was designed for 10 ms AC-mains half cycles. However, at 50 Hz, the measured duration of the positive semi cycle is 9.882 ms and the duration of the negative one is 10.118 ms (Fig. 9b). This lack of symmetry causes a decrease in the performance of the pre-calculated system without a frequency loop (option (a)) When the controller dynamically adapts to the measured duration of the half cycles (options (c) and (f)) or when a specifically duty cycle vector is generated (method (h)), the obtained results improve the result obtained by the pre-calculated system without any frequency loop (option (a)).

This lack of symmetry also justifies the decrease of performance when any of the frequency loops uses the duration of the previous half cycle to rectify the next one. Figure 9e shows the deterioration of the current waveform when options (b) or (e) are being applied. In this example, the frequency loop is applying 989 PWM cycles to a half cycle that lasts 10.11 ms, and vice versa. When the average of the last half cycles is used, option (d) and (g), the frequency loop applies 1000 PWM cycles to both half cycles: the one that lasts 9.89 ms and the one that lasts 10.11 ms. This is the same behavior as the original controller has, leading to similar results (Fig. 9b, k).

This lack of symmetry is usually observed when using AC power sources. The difference is less significant in the electrical grid. However, it still occurs so distinguishing positive and negative utility periods is recommended.

The second and main point of discussion is the performance of a pre-calculated controller with and without a frequency loop. The distortion of the input current can be observed in Fig. 9a and c for the pre-calculated system without a frequency loop obtaining low PF values.

Figure 9d and f show the behavior of the frequency loops when the last measure is considered to modify the utility vector (both the skip-repeat and the interpolation approaches obtained equivalent results). As expected, the PF and the input current THD do not reach their maximum values, but the ones obtained in nominal conditions are maintained. The loop is adapting to the new AC frequencies but the asymmetry of the input voltage is not compensated. This behavior is also observed using the average of the duration of the last half cycles, options (d) and (g), presented in Fig. 9j and l. The results obtained at nominal conditions are maintained when the input frequency is modified.

Finally, when both the variation of the input frequency and the asymmetry are considered, options (c), (f) (Fig. 9g, h, i) and the base line, option (h) (Fig. 9m, n, o) the PF and the input current THD reach the best observed values. The waveforms are very similar to those observed with the base line system, and also the PF and the THD (Table 4) are equivalent. Furthermore, the difference between the skip-repeat method and the interpolation one is negligible in terms of PF and THD. Therefore, the skip-repeat method is recommended, as it uses less hardware resources.

## 6 Conclusion

This work proposes the use of a simple frequency loop for pre-calculated PFC controllers. These controllers rely on a pre-calculated vector of PWM duty cycles that are applied along the utility period, relying on the zero-crossing detection as the only synchronization information. Any variation of the AC-mains half cycles duration decrements the obtained PF. The frequency loop generates a new duty cycle vector based on the original one by means of one of two possible alternatives: skipping-repeating the original duty cycle values or generating new duty cycle values by means of interpolation of the original ones. Both alternatives show similar results regarding PF and input current THD. However, the lower hardware requirements of the skip-repeat approach makes it a better option.

The experiments show that the frequency loop keeps the PF and the input current THD of the switching converter when the input voltage frequency is not in nominal conditions. This situation is described in the standard EN50160, which defines tolerance ranges for the AC-mains frequency of 50 Hz + 4%/−6%. A similar phenomenon is observed when there is a low precision in the clock of the controller signal, not providing the expected frequency. Furthermore, voltage unbalance, together with the presence of even harmonics can generate asymmetries between the positive and the negative semi cycles. These circumstances result on a deterioration of the PF and THD for any pre-calculated system without a frequency loop. Considering the low impact on the development, the minimal required resources of a frequency loop and the potential benefits, a skip-repeat frequency loop is recommended.

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