Abstract
Cycle time reduction is one of the most critical issues in gaining a competitive advantage in wafer fabrication. People widely recognize that lot size reduction can effectively shorten production cycle time. Due to the constraints of conventional equipment and technology, this concept has not been widely applied in wafer fabrication. However, because of the invention of new technology, restrictions on equipment and processes have been reduced in recent years. Wafer lot sizing policy thus becomes an alternative in reducing cycle time. This study develops a simulation model which can acquire optimal lot size to reduce cycle time under different bottleneck loading environments. Simulation experiments based on realistic data from a Taiwan semiconductor fabricator are conducted. Sensitivity analyses of lot sizing impact upon cycle time reduction in wafer fabrication are performed as well. Numerical results demonstrate that the proposed model is sound in acquiring the optimal lot size for cycle time reduction in different loading scenarios. The model can help fabrication managers obtain optimal lot sizes in different bottleneck situations to effectively reduce product cycle time.
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References
Koike A, Tsunematsu M (1995) Trend in semiconductor device production lines and processing equipment. Hitachi Rev 44(2):71–78
Luss H, Rosenwein MB (1990) A lot-sizing model for just-in-time manufacturing. J Oper Res Soc 41(3):201–209
Trigeiro WW, Thomas LJ, McClain JO (1989) Capacitated lot sizing with setup times. Manage Sci 35(3):353–366
Banerjee A, Burton JS (1990) Single and multistage production lot sizing with work-in-process inventory considerations. Eng Costs Prod Econ 19:287–294
Moon I (1994) Multiproduct economic lot size models with investment costs for setup reduction and quality improvement: review and extension. Int J Prod Res 32(12):2795–2801
Lee HL (1992) Lot sizing to reduce capacity utilization in a production process with defective items, process corrections, and rework. Manage Sci 38(9):1314–1328
Carmon TF, Nahmias S (1994) A preliminary model for lot sizing in semiconductor manufacturing. Int J Prod Econ 35:259–264
Ponnambalam SG, Reddy MM (2003) A GA-SA multiobjective hybrid search algorithm for integrating lot sizing and sequencing in flow-line scheduling. Int J Adv Manuf Technol 21(2):126–137
Prasad PSS, Chetty OVK (2001) Multilevel lot sizing with a genetic algorithm under fixed and rolling horizons. Int J Adv Manuf Technol 18:520–527
Ouenniche J, Boctor FF (2001) The multi-product, economic lot-sizing problem in flow shops: the powers-of-two heuristic. Comput Oper Res 28:1165–1182
Connors DP, Feigin GE, Yao DD (1996) A queuing network model for semiconductor manufacturing. IEEE Trans Semicond Manuf 9(3):412–427
Ouenniche J, Boctor FF (2001) The two-group heuristic to solve the multi-product, economic lot sizing and scheduling problem in flow shops. Eur J Oper Res 129:539–554
Byrne MD (1990) Multi-item production lot sizing using a search simulation approach. Eng Costs Prod Econ 19:307–311
Byrne MD, O’Grady P (1990) An industrial study of the effects of batch sizes on the performance of the overall manufacturing system. Eng Costs Prod Econ 19:139–147
Shanthakumar P (1992) Simulation the impact of process capability on lot sizes in batch manufacturing. Int J Prod Econ 26:203–210
Bonnin O, Mercier D, Levy D, Henry M, Pouilloux I, Mastromatteo E (2003) Single-wafer/mini-batch approach for fast cycle time in advanced 300-mm fabrication. IEEE Trans Semicond Manuf 16(2):111–120
Nagaraj P, Selladurai V (2002) Analysis of optimum batch size in multistage, multifacility and multiproduct manufacturing systems. Int J Adv Manuf Technol 19(2):117–124
Savsar M (1997) Simulation analysis of a pull-push system for an electronic assembly line. Int J Prod Econ 51:205–214
Berkley BJ (1996) A simulation study of container size in two-card kanban systems. Int J Prod Res 34(12):3417–3445
Collins DW, Williams K, Dye B (2005) Getting ready for the simulation revolution in 300 mm fabrication productivity. Proceedings of IEEE international symposium on semiconductor manufacturing, Tokyo, Japan, pp 348–351
Gary SM, Costas JS (2006) Fundamentals of semiconductor manufacturing and process control. Wiley, New Jersey
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Wang, CN., Wang, CH. A simulated model for cycle time reduction by acquiring optimal lot size in semiconductor manufacturing. Int J Adv Manuf Technol 34, 1008–1015 (2007). https://doi.org/10.1007/s00170-006-0884-9
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DOI: https://doi.org/10.1007/s00170-006-0884-9