Machine Vision and Applications

, Volume 24, Issue 2, pp 371–392 | Cite as

FPGA-based detection of SIFT interest keypoints

  • Leonardo ChangEmail author
  • José Hernández-Palancar
  • L. Enrique Sucar
  • Miguel Arias-Estrada
Original Paper


The use of local features in images has become very popular due to its promising results. They have shown significant benefits in a variety of applications such as object recognition, image retrieval, robot navigation, panorama stitching, and others. SIFT is one of the local features methods that have shown better results. Among its main disadvantages is its high computational cost. In order to speedup this algorithm, this work proposes the design and implementation of an efficient hardware architecture based on FPGAs for SIFT interest point detection In order to take full advantage of the parallelism in this algorithm and to minimize the device area occupied by its implementation in hardware, part of the algorithm was reformulated. The main contribution of the hardware architecture proposed in this paper and the main difference with the rest of the architectures reported in the literature is that as the number of octaves to be processed is increased, the amount of occupied device area remains almost constant. The evaluations and experiments to the architecture support this contribution, as well as accuracy, repeatability, and distinctiveness of the results. Experiments also showed device area occupation and time constraints of the hardware implementation. The architecture presented in this paper is able to detect interest points in an image of 320 × 240 in 11 ms, which represents a speedup of 250 × with respect to a software implementation.


Local features SIFT Keypoint detection Hardware architecture FPGA 


  1. 1.
    Atmel: 3x3 convolver with run-time reconfigurable vector multiplier in Atmel at6000 FPGAs. (1999)
  2. 2.
    Bay H., Ess A., Tuytelaars T., Van Gool L.: Speeded-up robust features (SURF). Comput. Vis. Image Underst. 110(3), 346–359 (2008). doi: 10.1016/j.cviu.2007.09.014 CrossRefGoogle Scholar
  3. 3.
    Bonato V., Marques E., Constantinides G.A.: A parallel hardware architecture for scale and rotation invariant feature detection. IEEE Trans Circuits Syst Video Technol 18(12), 1703–1712 (2008). doi: 10.1109/TCSVT.2008.2004936 CrossRefGoogle Scholar
  4. 4.
    Bonato, V., Marques, E., Constantinides, G.A.: A parallel hardware architecture for image feature detection. In: ARC’08: Proceedings of the 4th international workshop on reconfigurable computing, pp. 137–148. Springer, Berlin (2008)Google Scholar
  5. 5.
    Bradski, G.: The OpenCV Library. Dr. Dobb’s Journal of Software Tools (2000)Google Scholar
  6. 6.
    Chati, H.D., Muhlbauer, F., Braun, T., Bobda, C., Berns, K.: Hardware/software co-design of a key point detector on FPGA. In: FCCM’07: proceedings of the 15th annual IEEE symposium on field-programmable custom computing machines, pp. 355–356. IEEE Computer Society, Washington (2007). doi: 10.1109/FCCM.2007.36
  7. 7.
    Evans, J.: Efficient FIR filter architectures suitable for FPGA implementation (1994).
  8. 8.
    Grabner, M., Grabner, H., Bischof, H.: Fast Approximated SIFT. In: Narayanan, P.J., Nayar, S.K., Shum, H.Y. (eds.) ACCV (1), Lecture Notes in Computer Science, vol. 3851, pp. 918–927. Springer, Berlin (2006)Google Scholar
  9. 9.
    Herbordt M.C., VanCourt T., Gu Y., Sukhwani B., Conti A., Model J., DiSabello D.: Achieving High Performance with FPGA-Based Computing. Computer 40(3), 50–57 (2007). doi: 10.1109/MC.2007.79 CrossRefGoogle Scholar
  10. 10.
    Heymann, S., Frhlich, B., Medien, F., Müller, K., Wiegand, T.: SIFT implementation and optimization for general-purpose GPU. In: In WSCG07 (2007)Google Scholar
  11. 11.
    Ke, Y., Sukthankar, R.: PCA-SIFT: a more distinctive representation for local image descriptors. In: 2004 IEEE Computer Society Conference on Computer Vision and Pattern Recognition, vol. 2, pp. 506–513 (2004). doi: 10.1109/CVPR.2004.1315206
  12. 12.
    Lalonde, M., Byrns, D., Gagnon, L., Teasdale, N., Laurendeau, D.: Real-time eye blink detection with GPU-based SIFT tracking. In: CRV’07: Proceedings of the Fourth Canadian Conference on Computer and Robot Vision, pp. 481–487. IEEE Computer Society, Washington (2007). doi: 10.1109/CRV.2007.54
  13. 13.
    Lowe D.G.: Distinctive image features from scale-invariant keypoints. Int. J. Comput. Vis. 60(2), 91–110 (2004). doi: 10.1023/B:VISI.0000029664.99615.94 CrossRefGoogle Scholar
  14. 14.
    Mikolajczyk K., Schmid C.: A performance evaluation of local descriptors. IEEE Trans. Pattern Anal. Mach. Intell. 27(10), 1615–1630 (2005). doi: 10.1109/TPAMI.2005.188 CrossRefGoogle Scholar
  15. 15.
    Pettersson, N., Petersson, L.: Online stereo calibration using FPGAs. In: Proceedings of IEEE Intelligent vehicles symposium, 2005, pp. 55–60 (2005)Google Scholar
  16. 16.
    Pratt W.K., Adams J.E.: Digital image processing, 4th edn. J. Electron. Imaging 16(2), 029901 (2007)CrossRefGoogle Scholar
  17. 17.
    Qiu, J., Huang, T., Ikenaga, T.: 1D-based 2D Gaussian Convolution Unit Based Hardware Accelerator for Gaussian & DoG Pyramid Construction in SIFT. In: Proceedings of the IEICE General Conference 2009(2), 178 (2009-03-04).
  18. 18.
    Qiu, J., Huang, T., Ikenaga, T.: A 7-Round Parallel Hardware-Saving Accelerator for Gaussian and DoG Pyramid Construction Part of SIFT. In: ACCV09, pp. III: 75–84 (2010)Google Scholar
  19. 19.
    Se, S., Kong Ng, H., Jasiobedzki, P., jing Moyung, T.: Vision based modeling and localization for planetary exploration rovers. In: 55th International Astronautical Congress 2004 (2004)Google Scholar
  20. 20.
    Sinha, S., Frahm, J.M., Pollefeys, M., Genc, Y.: Feature tracking and matching in video using programmable graphics hardware. Mach. Vis. Appl. doi: 10.1007/s00138-007-0105-z
  21. 21.
    Sinha, S., Frahm, J.m., Pollefeys, M., Genc, Y.: GPU-based Video Feature Tracking and Matching. Tech. rep. (2006).
  22. 22.
    Tuytelaars T., Mikolajczyk K.: Local invariant feature detectors: a survey. Now Publishers Inc., Hanover (2008)Google Scholar
  23. 23.
    Vadlamani, S., Mahmoud, W.: Comparison of CORDIC algorithm implementations on FPGA families. In: System Theory, 2002. Proceedings of the Thirty Fourth Southeastern Symposium on, pp. 192–196 (2002)Google Scholar
  24. 24.
    Vedaldi, A.: An open implementation of the SIFT detector and descriptor. Tech. Rep. 070012, UCLA CSD (2007)Google Scholar
  25. 25.
    Wu, C.: SiftGPU: A GPU implementation of scale invariant feature transform (SIFT). (2007)

Copyright information

© Springer-Verlag 2012

Authors and Affiliations

  • Leonardo Chang
    • 1
    Email author
  • José Hernández-Palancar
    • 1
  • L. Enrique Sucar
    • 2
  • Miguel Arias-Estrada
    • 2
  1. 1.Advanced Technologies Application CenterHavanaCuba
  2. 2.National Institute for Astrophysics, Optics and ElectronicsPueblaMexico

Personalised recommendations