Abstract
The article presents two multipliers equipped with error compensation techniques, utilizing approximate 4:2 compressors to minimize energy consumption. Compared to previous approximate multipliers with error compensation circuit, the proposed designs named, “M00” and “M01”, strike a good balance between accuracy and energy consumption. Although the reduction in the number of transistors has significantly decreased the energy consumption of M00, the accuracy of this design is still more than adequate for real-world applications such as image processing and neural networks. On the other hand, M01 attains high precision while consuming less energy than other multipliers. This article compares the proposed designs with existing multipliers using HSPICE tool in 7 nm FinFET technology. Moreover, the accuracy and quality of the proposed multipliers are evaluated using MATLAB. The results reveal that both proposed designs are very efficient in image processing. According to the results, M00 has the lowest energy consumption among the considered designs. M00 is about 7% better than its counterpart in terms of the power-delay-product parameter (5% Pdynamic and 48% Pstatic). M01 presents favorable results in the sharpening, smoothing, and Discrete Cosine Transform processes.
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Data Availability
The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.
References
F. Ahmadi, M.R. Semati, H. Daryanavard, A low-power improved-accuracy approximate error-report-propagate adder for DSP applications. Circuits, Syst. Signal Process. 42(6), 3744–3769 (2023). https://doi.org/10.1007/s00034-023-02291-9
F. Ahmadi, M.R. Semati, H. Daryanavard, A. Minaeifar, Energy-efficient approximate full adders for error-tolerant applications. Comput. Electr. Eng. 110, 108877 (2023). https://doi.org/10.1016/j.compeleceng.2023.108877
M. Ahmadinejad, M.H. Moaiyeri, Energy-and quality-efficient approximate multipliers for neural network and image processing applications. IEEE Trans. Emerg. Topics Comput. 10(2), 1105–1116 (2021)
O. Akbari, M. Kamal, A. Afzali-Kusha, M. Pedram, Dual-quality 4: 2 compressors for utilizing in dynamic accuracy configurable multipliers. IEEE Trans. Very Large Scale Integr. VLSI Syst. 25(4), 1352–1361 (2017)
P. Anguraj, T. Krishnan, S. Subramanian, CMOS implementation and performance analysis of known approximate 4: 2 compressors. J. Electron. Test. 38(4), 353–370 (2022)
S. Chandaka, B. Narayanam, Hardware efficient approximate multiplier architecture for image processing applications. J. Electr. Testing 38(2), 1–14 (2022)
P.J. Edavoor, S. Raveendran, A.D. Rahulkar, Approximate multiplier design using novel dual-stage 4: 2 compressors. IEEE Access 8, 48337–48351 (2020)
S.A.H. Ejtahed, S. Timarchi, Efficient approximate multiplier based on a new 1-Gate approximate compressor. Circ. Syst. Signal Process. 41(5), 2699–2718 (2022)
D. Esposito, A.G.M. Strollo, E. Napoli, D. De Caro, N. Petra, Approximate multipliers based on new approximate compressors. IEEE Trans. Circ. Syst. I Regul. Pap. 65(12), 4169–4182 (2018)
B. Fang et al., Approximate multipliers based on a novel unbiased approximate 4–2 compressor. Integration 81, 17–24 (2021)
V. Gupta, D. Mohapatra, A. Raghunathan, K. Roy, Low-power digital signal processing using approximate adders. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 32(1), 124–137 (2012)
M. Ha, S. Lee, Multipliers with approximate 4–2 compressors and error recovery modules. IEEE Embed. Syst. Lett. 10(1), 6–9 (2017)
S.-F. Hsiao, M.-R. Jiang, J.-S. Yeh, Design of high-speed low-power 3–2 counter and 4–2 compressor for fast multipliers. Electron. Lett. 34(4), 341–342 (1998)
U.A. Kumar, S.K. Chatterjee, S.E. Ahmed, Low-power compressor-based approximate multipliers with error correcting module. IEEE Embed. Syst. Lett. 14(2), 59–62 (2021)
M.H. Moaiyeri, F. Sabetzadeh, S. Angizi, An efficient majority-based compressor for approximate computing in the nano era. Microsyst. Technol. 24(3), 1589–1601 (2018)
M. Pashaeifar, M. Kamal, A. Afzali-Kusha, M. Pedram, Approximate reverse carry propagate adder for energy-efficient DSP applications. IEEE Trans. Very Large Scale Integr. VLSI Syst. 26(11), 2530–2541 (2018)
H. Pei, X. Yi, H. Zhou, Y. He, Design of ultra-low power consumption approximate 4–2 compressors based on the compensation characteristic. IEEE Trans. Circ. Syst. II Express Briefs 68(1), 461–465 (2020)
A. Sadeghi, N. Shiri, M. Rafiee, A. Darabi, E. Abiri, Voltage over-scaling CNT-based 8-bit multiplier by high-efficient GDI-based counters. IET Comput. Digital Techn. 17(1), 1–19 (2022)
A. Sadeghi, N. Shiri, M. Rafiee, High-efficient, ultra-low-power and high-speed 4: 2 compressor with a new full adder cell for bioelectronics applications. Circ. Syst. Signal Process. 39(12), 6247–6275 (2020)
F. Salmanpour, M.H. Moaiyeri, F. Sabetzadeh, Ultra-compact imprecise 4: 2 compressor and multiplier circuits for approximate computing in deep nanoscale. Circ. Syst. Signal Process. 40(9), 4633–4650 (2021)
S. Shirkavand Saleh Abad, M.H. Moaiyeri, A hardware-and accuracy-efficient approximate multiplier with error compensation for neural network and image processing applications. Circ. Syst. Signal Process. 41(12), 1–20 (2022)
N.M. Sk, Low power, high speed approximate multiplier for error resilient applications. Integration 84, 37–46 (2022)
A. G. Strollo, D. De Caro, E. Napoli, N. Petra, G. Di Meo, Low-power approximate multiplier with error recovery using a new approximate 4–2 compressor. in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–4, (2020).
A.G.M. Strollo, E. Napoli, D. De Caro, N. Petra, G. Di Meo, Comparison and extension of approximate 4–2 compressors for low-power approximate multipliers. IEEE Trans. Circ. Syst. I Regul. Pap. 67(9), 3021–3034 (2020)
A.G.M. Strollo, E. Napoli, D. De Caro, N. Petra, G. Saggese, G. Di Meo, Approximate multipliers using static segmentation: error analysis and improvements. IEEE Trans. Circ. Syst. I Regul. Pap. 69(6), 2449–2462 (2022)
Z. Wang, A.C. Bovik, H.R. Sheikh, E.P. Simoncelli, Image quality assessment: from error visibility to structural similarity. IEEE Trans. Image Process. 13(4), 600–612 (2004)
Z. Yang, J. Han, F. Lombardi, Approximate compressors for error-resilient multiplier design. in 2015 IEEE International symposium on defect and fault tolerance in VLSI and nanotechnology systems (DFTS), IEEE, pp. 183–186 (2015).
P. Zakian, R.N. Asli, An efficient design of low-power and high-speed approximate compressor in FinFET technology. Comput. Electr. Eng. 86, 106651 (2020)
Y. Zhang, X. Chen, C. He, G. Xie, Energy-efficient multipliers using imprecise compressors for image multiplication. Int. J. Circ. Theory Appl. 50, 11 (2022)
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Minaeifar, A., Abiri, E., Hassanli, K. et al. A High-Accuracy Low-Power Approximate Multipliers with New Error Compensation Technique for DSP Applications. Circuits Syst Signal Process 43, 526–544 (2024). https://doi.org/10.1007/s00034-023-02487-z
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DOI: https://doi.org/10.1007/s00034-023-02487-z