Skip to main content
SpringerLink
Log in

In-Memory Computing with 6T SRAM for Multi-operator Logic Design

  • Short Paper
  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

This article presents a reconfigurable in-/near-memory advanced computing (InMAC) architecture based on 6T SRAM, with a storage capacity of 1 KB (128 \(\times \) 64). The proposed architecture utilizes standard 65 nm CMOS technology and operates with a power supply of 1 V. Along with standard storage operations, the design performs various complex Boolean computing operations, such as binary to gray, gray to binary, 2’s complement, and binary addition, with 8-bit precision. The architecture also implements other essential logic operations, such as NAND, NOR, XOR, and XNOR, in an area-efficient manner, without requiring complex circuitry. The design offers flexibility in the reconfiguration to meet specific bit precision and operation requirements. In-memory computing approaches improve the latency by 7 \(\times \) and 4 \(\times \) for logic implementation and Boolean computation, respectively, compared to conversions performed outside the macro. Additionally, the optimized full adder design outperforms the state-of-the-art design in terms of all parameters analyzed, with reductions of 40% in the number of transistors, 25.4% in latency, 55.2% in dynamic power, and 28.1% in static power. The proposed InMAC architecture can potentially use in-memory computing in various applications that require advanced computing with low latency.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

Data Availability

Data sharing does not apply to this article as no datasets were generated or analyzed during the current study, and detailed circuit simulation results are given in the manuscript.

References

  1. A. Agrawal, A. Jaiswal, C. Lee, K. Roy, X-SRAM: enabling in-memory Boolean computations in CMOS static random access memories. IEEE Trans. Circuits Syst. I Regul. Pap. 65, 4219–4232 (2018)

    Article  Google Scholar 

  2. K. Akyel, H. Charles, J. Mottin, B. Giraud, G. Suraci, S. Thuries, J. Noel, DRC2: dynamically reconfigurable computing circuit based on memory architecture, in IEEE International Conference on Rebooting Computing (ICRC) (2016), pp. 1–8

  3. M. Ali, A. Jaiswal, S. Kodge, A. Agrawal, I. Chakraborty, K. Roy, IMAC: in-memory multi-bit multiplication and accumulation in 6T SRAM array. IEEE Trans. Circuits Syst. I Regul. Pap. 67, 2521–2531 (2020)

    Article  Google Scholar 

  4. H. Chen, J. Li, C. Hsu, C. Sun, Configurable 8T SRAM for enabling in-memory computing, in International Conference on Communication Engineering and Technology (ICCET) (2019), pp. 139–142

  5. Y. Chen, L. Lu, B. Kim, T. Kim, Reconfigurable 2T2R ReRAM architecture for versatile data storage and computing in-memory. IEEE Trans. Very Large Scale Integr. VLSI Syst. 28, 2636–2649 (2020)

    Article  Google Scholar 

  6. Y. Chuang, H. Ou, B. Liu, A novel bubble tolerant thermometer-to-binary encoder for flash A/D converter, in (IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT) (2005), pp. 315–318

  7. Q. Dong, S. Jeloka, M. Saligane, Y. Kim, M. Kawaminami, A. Harada, S. Miyoshi, D. Blaauw, D. Sylvester, A 0.3V VDDmin 4+2T SRAM for searching and in-memory computing using 55 nm DDC technology, in Symposium on VLSI Circuits (2017), pp. C160–C161

  8. S. Jeloka, N. Akesh, D. Sylvester, D. Blaauw, A 28 nm configurable memory (TCAM/BCAM/SRAM) using push-rule 6T bit cell enabling logic-in-memory. IEEE J. Solid-State Circuits 51, 1009–1021 (2016)

    Article  Google Scholar 

  9. N. Muralimanohar, R. Balasubramonian, N. Jouppi, Cacti 6.0: A Tool to Understand Large Caches. Accessed 2008

  10. A. Rajput, M. Pattanaik, Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation. Microelectron. J. 137, 105795 (2023)

    Article  Google Scholar 

  11. A. Sebastian, T. Tomas, N. Papandreou, M. Le Gallo, L. Kull, T. Lukas, E.E. Parnell, Temporal correlation detection using computational phase-change memory. Nat. Commun. 8, 1115 (2017)

    Article  Google Scholar 

  12. V. Sharma, P. Bisht, A. Dalal, M. Gopal, S. Vishvakarma, S. Chouhan, Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications. AEU Int. J. Electron. Commun. 104, 10–22 (2019)

    Article  Google Scholar 

  13. V. Sharma, J. Kim, H. Kim, L. Lu, T. Kim, A reconfigurable 16Kb and 8T SRAM macro with improved linearity for multibit compute-in memory of artificial intelligence edge devices. IEEE J. Emerg. Select. Top. Circuits Syst. 12, 522–535 (2022)

    Article  Google Scholar 

  14. V. Sharma, N. Gupta, A. Shah, S. Vishvakarma, S. Chouhan, A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes. Analog Integr. Circ. Sig. Process. 107, 339–352 (2021)

    Article  Google Scholar 

  15. X. Si, J. Chen, Y. Tu, W. Huang, J. Wang, Y. Chiu, W. Wei, S. Wu, X. Sun, R. Liu, S. Yu, R. Liu, C. Hsieh, K. Tang, Q. Li, M. Chang, A twin-8T SRAM computation-in-memory unit-macro for multibit CNN-based AI edge processors. IEEE J. Solid State Circuits 55, 189–202 (2020)

    Article  Google Scholar 

  16. X. Si, W. Khwa, J. Chen, J. Li, X. Sun, R. Liu, S. Yu, H. Yamauchi, Q. Li, M. Chang, A dual-split 6T SRAM-based computing-in-memory unit-macro with fully parallel product-sum operation for binarized DNN edge processors. IEEE Trans. Circuits Syst. I Regul. Pap. 66, 4172–4185 (2019)

    Article  Google Scholar 

  17. K. Soundrapandiyan, S. Vishvakarma, B. Reniwal, Enabling energy-efficient in-memory computing with robust assist-based reconfigurable sense amplifier in SRAM array. IEEE J. Emerg. Select. Top. Circuits Syst. 13, 445–455 (2023)

    Article  Google Scholar 

  18. T. Tsai, J. Li, C. Hsu, and C. Sun, Testing of in-memory-computing 8T SRAMs, in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2019), pp. 1–4

  19. S. Yin, Z. Jiang, J. Seo, M. Seok, XNOR-SRAM: in-memory computing SRAM macro for binary/ternary deep neural networks. IEEE J. Solid State Circuits 55, 1733–1743 (2020)

    Google Scholar 

  20. C. Yu, T. Yoo, T. Kim, K. Tshun Chuan, B. Kim, A 16K current-based 8T SRAM compute-in-memory macro with decoupled read/write and 1-5 bit column ADC, in IEEE Custom Integrated Circuits Conference (CICC) (2020), pp. 1–4

  21. J. Zhang, Z. Wang, N. Verma, In-memory computation of a machine-learning classifier in a standard 6T SRAM array. IEEE J. Solid State Circuits 52, 915–924 (2017)

    Article  Google Scholar 

Download references

Acknowledgements

The work was supported in part by the Science & Engineering Research Board (SERB), Govt. of India under project SB/S9/Z-03/2017-XVIII (2020-21) and in part by the CHANAKYA Fellowship of IITI DRISHTI Foundation under the National Mission on Interdisciplinary Cyber Physical System (NM-ICPS) of Department of Science and Technology, Government of India.

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, IIT Indore, Indore, India

    Narendra Singh Dhakad, Eshika Chittora, Gopal Raut & Santosh Kumar Vishvakarma

  2. Nanyang Technological University, Singapore, Singapore

    Vishal Sharma

Authors
  1. Narendra Singh Dhakad
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Eshika Chittora
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Gopal Raut
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Vishal Sharma
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Santosh Kumar Vishvakarma
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Santosh Kumar Vishvakarma.

Ethics declarations

Conflict of interest

There is no conflict of interest from the authors.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Dhakad, N.S., Chittora, E., Raut, G. et al. In-Memory Computing with 6T SRAM for Multi-operator Logic Design. Circuits Syst Signal Process 43, 646–660 (2024). https://doi.org/10.1007/s00034-023-02481-5

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-023-02481-5

Keywords

Search

Navigation