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A Novel Wide Tuning Range Differential Ring Oscillator Application in Dynamically Stable and 1.17 \(\upmu \)s Lock Time CP-PLL Frequency Synthesizer

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Abstract

A novel delay cell circuit for differential ring oscillator (DRO) with large tuning range along with application in charge pump phase lock loop (CP-PLL) frequency synthesizer has been presented in this paper. Using 0.18\(\mu \)m CMOS technology with power supply of 1.8 V, the two DRO architectures: 3-stage and 5-stage, were built and simulated. In both 3-stage and 5-stage DROs, single controlled voltage is employed. The suggested 3-stage and 5-stage DRO circuits generate a tuning range of 96.77 MHz\(-\)5.296 GHz and 36.33 MHz\(-\)2.803 GHz, respectively. The % total harmonic distortion (%THD) of both DRO architectures is also evaluated. The suggested 3-stage and 5-stage DROs consume 6.63 mW and 11.05 mW power at an oscillation frequency of 4.76 GHz and 2.479 GHz, respectively. At an offset frequency of 10 MHz from the oscillation frequency, the proposed circuits have phase noise of \(-\)119.93 dBc/Hz and \(-\)128.24 dBc/Hz, respectively. The layout of proposed design has been drawn and pre- and post-layout simulation results show satisfactory variations of tuning range and phase noise of proposed design. The suggested circuit’s robustness is verified with the help of PVT and Monte Carlo analysis. When compared to contemporary research, the proposed DROs have the widest tuning range. Proposed DRO application in CP-PLL frequency synthesizer has locking time of 1.17 \(\upmu \)s and shows good settling behaviour with dynamic parameter variations.

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Data Availability

The datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.

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Acknowledgements

This research is supported by the Regional Academic Center for Space (RAC-S) sponsored research project. The Grant is received under RAC-S project RAC-S/PRO/21-22/01 at MNIT Jaipur. The authors are grateful to the RAC-S sponsored project, MNIT Jaipur, for providing the support to carry out the present research.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Malaviya National Institute of Technology Jaipur, Jaipur, Rajasthan, 302017, India

    Riyaz Ahmad & Dharmendar Boolchandani

  2. Department of Electronics and Communication Engineering, GLA University, Mathura, Uttar Pradesh, India

    Gaurav Kumar Sharma

  3. Semi-Conductor Laboratory, Chandigarh, Punjab, India

    Ashutosh Yadav

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  1. Riyaz Ahmad
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Ahmad, R., Sharma, G.K., Boolchandani, D. et al. A Novel Wide Tuning Range Differential Ring Oscillator Application in Dynamically Stable and 1.17 \(\upmu \)s Lock Time CP-PLL Frequency Synthesizer. Circuits Syst Signal Process 42, 7045–7072 (2023). https://doi.org/10.1007/s00034-023-02466-4

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