Abstract
This paper presents a pseudo-random binary sequence (PRBS) generator using merged XOR-D flip-flop as building blocks. The proposed architecture uses differential cascode voltage switch logic (DCVSL)-based dynamic XOR gate. The cross-coupled architecture of the pull-up network creating positive feedback in the DCVSL XOR gate is used as a latch by adding a transistor to apply a clock signal. This arrangement reduces the requirement of one latch in a master–slave D flip-flop (MS-DFF) from each lane. It reduces the area occupied in the layout and power requirements for the PRBS generator. The post-layout simulation for the PRBS generator operating at 5 Gb/s is performed in the 65 nm CMOS technology with a 1 V supply voltage. The proposed PRBS generator requires 2.4 mW of power. The jitter is 5.6 ps for the worst-case output of the proposed PRBS generator. In the proposed merged XOR-D flip-flop, there is an improvement of 33.3%, 27.4%, 29.1%, and 31.2% in power, area, maximum operating frequency, and the number of transistors, respectively, compared to when both XOR gate and D flip-flop are used separately. The figure of merit is improved by 14.8% for the proposed PRBS generator.
Similar content being viewed by others
Data Availability
Data sharing is not applicable to this article as no data sets were generated or analyzed during the current study.
References
A. Amirany, K. Jafari, M.H. Moaiyeri, True random number generator for reliable hardware security modules based on a neuromorphic variation-tolerant spintronic structure. IEEE Trans. Nanotechnol. 19, 784–791 (2020). https://doi.org/10.1109/TNANO.2020.3034818
C.-H. Chang, J. Gu, M. Zhang, A review of 018\(\mu \)m full adder performances for tree structured arithmetic circuits. IEEE Trans. Very Large Scale /Integr. (VLSI) Syst. 13(6), 686–695 (2005). https://doi.org/10.1109/TVLSI.2005.848806
M. S. Chen, C. K. K. Yang, A low-power highly multiplexed parallel PRBS generator. In: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, (2012), pp. 1–4, https://doi.org/10.1109/CICC.2012.6330664
R. Clarke, M.R. LeRoy, S. Raman, T.G. Neogi, R.P. Kraft, J.F. McDonald, 140 Gb/s Serializer using clock doublers in 90 nm SiGe technology. IEEE J. Solid State Circuits 50(11), 2703–2713 (2015). https://doi.org/10.1109/JSSC.2015.2472600
R. Dayalu, Low-voltage low-power CMOS full adder. IET Proc. Circuits Dev. Syst. 148(1), 19–24 (2001). https://doi.org/10.1049/ip-cds:20010170
S. Goel, A. Kumar, M.A. Bayoumi, Design of robust, energy efficient full adders for deep-submicrometer design using hybrid-CMOS logic style. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(12), 1309–1321 (2006). https://doi.org/10.1109/TVLSI.2006.887807
P.K. Govindaswamy, V.S.R. Pasupureddi, A 2\(^7\)-1, 20-Gb/s, Low-power, charge-steering half-rate PRBS generator in 1.2 V, 65 nm CMOS. Circuits Syst. Signal Proc. 40, 5553–5571 (2021). https://doi.org/10.1007/s00034-021-01732-7
P. K. Govindaswamy, V. S. R. Pasupureddi, A 2\(^7\)-1 low-power half-rate 16-Gb/s charge-mode prbs generator in 1.2V, 65nm CMOS, In: 2020 IEEE Computer Society Annual Symp. on VLSI (ISVLSI), (2020), pp. 212–215, https://doi.org/10.1109/ISVLSI49217.2020.00046
J. Hallin, T. Kjellberg, T. Swahn, A 165-Gb/s 4:1 multiplexer in InP DHBT technology, In: IEEE Compound Semiconductor International Circuit Symposium 2005. CSIC ’05., Palm Springs, CA, USA, (2005), pp. 4 . https://doi.org/10.1109/CSICS.2005.1531833
L. Heller, W. Griffin, J. Davis, N. Thoma, Cascode voltage switch logic: a differential CMOS logic family, In: IEEE International Solid-State Circuits Conference Digest of Technical Papers, (1984), pp. 16–17, https://doi.org/10.1109/ISSCC.1984.1156629
J. Hu, Z. Zhang, Q. Pan, A \(15\, Gb/s 00037\, mm^{2}\) 0019 pJ/Bit full-rate programmable multi-pattern pseudo-random binary sequence generator, IEEE Trans. Circuits Syst. II Exp. Briefs 67(9), 1499–1503 (2020). https://doi.org/10.1109/TCSII.2020.3008567
J. Kandpal, A. Tomar, M. Agarwal, K.K. Sharma, High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR-XNOR cell. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 28(6), 1413–1422 (2020). https://doi.org/10.1109/TVLSI.2020.2983850
M.M. Khafaji, R. Henker, F. Ellinger, A 1 pJ/bit 80 Gb/s 2\(^{15}\)-1 PRBS generator with a modified Cherry-Hooper output driver. IEEE J. Solid-State Circuits 54(7), 2059–2069 (2019). https://doi.org/10.1109/JSSC.2019.2904172
F. Khodayari, A. Amirany, M.H. Moaiyeri, K. Jafari, A variation-aware ternary true random number generator using magnetic tunnel junction at subcritical current regime. IEEE Trans. Magn. 59(3), 1–8 (2023). https://doi.org/10.1109/TMAG.2022.3233891
J. K. Kim, J. Kim and D.K. Jeong “A 20 Gb/s full-rate 2\(^7\)-1 PRBS generator integrated with 20 GHz PLL in 0.13 \(\mu \)m CMOS”, In: IEEE Asian Solid-State Circuits Confernece, (2008). https://doi.org/10.1109/ASSCC.2008.4708768
E. Laskin, S.P. Voinigescu, A 60 mW per lane, 4\(\times \)23 Gb/s 2\(^7\)-1 PRBS generator. IEEE J. Solid State Circuits 41(10), 2198–2208 (2006). https://doi.org/10.1109/JSSC.2006.878112
M. Morsali, M.H. Moaiyeri, R. Rajaei, A process variation resilient spintronic true random number generator for highly reliable hardware security applications. Microelectron. J. 127, 105606 (2022)
P.K. Meher, Extended sequential logic for synchronous circuit optimization and its applications. IEEE Trans. Comput. Aid. Des Int. Circuits Syst. 28(4), 469–477 (2009). https://doi.org/10.1109/TCAD.2009.2014006
H. Naseri, S. Timarchi, Low-power and fast full adder by exploring new XOR and XNOR gates. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(8), 1481–1493 (2018). https://doi.org/10.1109/TVLSI.2018.2820999
H.J. Ng, R. Feger, A. Stelzer, A fully-integrated 77-GHz pseudo-random noise coded Doppler radar sensor with programmable sequence generators in SiGe technology, In: IEEE MTT-S International Microwave Symposium (IMS2014), Tampa, FL, USA, (2014), pp. 1–4, https://doi.org/10.1109/MWSYM.2014.6848382
J.J. O’Reilly, Series-parallel generation of m-sequences. Radio Electron. Eng. 45(4), 171–176 (1975). https://doi.org/10.1049/ecej:19960205
S. Ray, M.M. Hella, A 10 Gb/s Inductorless AGC amplifier With 40 dB linear variable gain control in 0.13 \(\mu \)m CMOS. IEEE J. Solid-State Circuits 51(2), 440–456 (2016). https://doi.org/10.1109/JSSC.2015.2496782
B. Razavi, The StrongARM latch [a circuit for all seasons]. IEEE Solid State Circuits Mag. 7(2), 12–17 (2015). https://doi.org/10.1109/MSSC.2015.2418155
M. Sakare, A Quarter-Rate 2\(^7\)-1 pseudo-random binary sequence generator using interleaved architecture, In: 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), (2016), pp. 196–201, https://doi.org/10.1109/VLSID.2016.35
M. Sakare, A power and area efficient architecture of a PRBS generator with multiple outputs. IEEE Trans. Circuits Syst. II Exp. Briefs 64(8), 927–931 (2017). https://doi.org/10.1109/TCSII.2016.2641582
J. Savoj, A.A. Abbasfar, A. Amirkhany, B.W. Garlepp, M.A. Horowitz, A new technique for characterization of digital-to-analog converters in high-speed systems, In: IEEE Design, Automation & Test in Europe Conference & Exhibition, (2007) https://doi.org/10.1109/DATE.2007.364630
G. Scotti, D. Bellizia, A. Trifiletti, G. Palumbo, Design of low voltage high-speed cml d-latches in nanometer CMOS technologies. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. (2017). https://doi.org/10.1109/TVLSI.2017.2750207
G. Scotti, D. Bellizia, A. Trifiletti, G. Palumbo, Design of low-voltage high-speed cml d-latches in nanometer CMOS technologies. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(12), 3509–3520 (2017). https://doi.org/10.1109/TVLSI.2017.2750207
M. Singh, M. Sakare, S. Gupta, Testing of high-speed DACs using PRBS generation with Alternate-Bit-Tapping, In: Design, Automation & Test in Europe, Grenoble, France, (2011), pp. 1–6, https://doi.org/10.1109/DATE.2011.5763066
M.K. Singh, P. Singh, D.M. Das and M. Sakare, A low power 8 \(\times \) 2\(^7-1\) PRBS generator using Exclusive-OR gate merged D flip-flops, In: IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Lansing, MI, USA, (2021), pp. 779–782, https://doi.org/10.1109/MWSCAS47672.2021.9531827
U. Singh, Lijun Li, M.M. Green, A 34Gb, s 2:1 MUX, CMU based on a distributed amplifier using 0.18, spl mu, m CMOS, In: Digest of Technical Papers, Symposium on VLSI Circuits, Kyoto. Japan 2005, pp. 132–135 (2005). https://doi.org/10.1109/VLSIC.2005.1469350
K.J. Sham, S. Bommalingaiahnapallya, M.R. Ahmadi, R. Harjani, A 3 \(\times \) 5 Gb/s multilane low-power 0.18 \(\mu {{m}}^2\) CMOS pseudo random bit sequence generator, IEEE Trans. Circuits Syst. II Exp. Briefs 55(5), 432–436 (2008). https://doi.org/10.1109/TCSII.2007.912696
T. Swahn, J. Hallin, T. Kjellberg, Design and Test of InP DHBT ICs for a 100 Gb/s demonstrator system, In: International Conference on Indium Phosphide and Related Materials Conference Proceedings, Princeton, NJ, USA, (2006), pp. 79–84, https://doi.org/10.1109/ICIPRM.2006.1634116
D.Z. Turker, S.P. Khatri, E. Sánchez-Sinencio, A DCVSL delay cell for fast low power frequency synthesis applications. IEEE Trans. Circuits Syst. I: Reg. Papers 58(6), 1225–1238 (2011). https://doi.org/10.1109/TCSI.2010.2103170
M.A. Valashani, S. Mirzakuchaki, A novel fast, low-power and high-performance XOR-XNOR cell, In: IEEE International Symposium on Circuits and Systems (ISCAS), (2016), pp. 694–697, https://doi.org/10.1109/ISCAS.2016.7527335
A.J. Vishnani, M.V. Dave, M.S. Baghini, D.K. Sharma, A fully on-chip throughput measurement system for multi-gigabits/s on-chip interconnects, In: 3rd Asia Symposium on Quality Electronic Design (ASQED), Kuala Lumpur, Malaysia, (2011), pp. 119–124, https://doi.org/10.1109/ASQED.2011.6111713
Y. Wang, M.D. Wei, R. Negra, Low Power, 11.8 Gbps 2\(^7\)-1 Pseudo-random bit sequence generator in 65 nm standard CMOS, In: 2019 26th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), (2019), pp. 318–321, https://doi.org/10.1109/ICECS46596.2019.8965019
M. Yektaei, M.B.G. Ghoushchi, PDP and TPD flexible MCML and MTCML ultralow-power and high-speed structures for wireless and wireline applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 28(8), 1782–1795 (2020). https://doi.org/10.1109/TVLSI.2020.2996544
K. Zhu, V. Saxena, From design to test: a high-speed PRBS. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(10), 2099–2107 (2018). https://doi.org/10.1109/TVLSI.2018.2834373
Funding
This work is supported by Government of India under SERB-CRG (CRG/2021/008273) scheme.
Author information
Authors and Affiliations
Corresponding author
Ethics declarations
Conflicts of interest
We have no conflict of interests/competing interests to disclose.
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
About this article
Cite this article
Singh, M.K., Singh, P., Chichhula, U. et al. A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks. Circuits Syst Signal Process 42, 6813–6828 (2023). https://doi.org/10.1007/s00034-023-02425-z
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-023-02425-z