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Test Node Selection for Fault Diagnosis in Analog Circuits using Faster RCNN Model

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Abstract

Test node selection for finding faults in complex analog circuits is essential in fault dictionary techniques to reduce test cost in terms of time, to reduce the number of input variables of the circuit under test required for faults detection, and hence to minimize fault dictionary size. The proposed faster regional convolutional neural network-based test node selection procedure evaluates the relationship between the input variables (node voltage) using correlation measures to choose test nodes for fault diagnosis. A fault dictionary is built by measuring node voltages for different fault cases. For the given fault dictionary, initially the correlation coefficient of input variables is determined and the node correlation matrix is obtained. Test node selection proposed here determines the minimum number of nodes required for testing by finding the nodes with the highest number of zero correlations. Then the node correlation matrix is updated by removing the minimum nodes identified, and the nodes with the highest number of zero and weak correlation are found from the updated node correlation matrix for better fault coverage. Simulation results are presented by considering both hard and soft faults cases, and the performance of the proposed approach is evaluated using fault detection efficiency of test nodes of CUT. The comparative analysis is carried out for the proposed approach and various other techniques by evaluating various metrics, namely the computational time, accuracy, precision, recall, f-measure and specificity. The computational time and the accuracy rate attained by the proposed approach are 0.2 s and 97.4%, respectively.

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The data presented in this study are available on request from the corresponding author.

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  1. Department of Electronics and Communication Engineering, Coimbatore Institute of Technology, Coimbatore, India

    G. Puvaneswari

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Puvaneswari, G. Test Node Selection for Fault Diagnosis in Analog Circuits using Faster RCNN Model. Circuits Syst Signal Process 42, 3229–3254 (2023). https://doi.org/10.1007/s00034-022-02276-0

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