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A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder

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Abstract

Low-power and high-speed calculation is very important nowadays for energy-efficient demand of electronic devices. With the usage of ANT (All-N-transistor) logic, the speed constraint caused by PMOS transistors can be overcome through an auxiliary current path across NMOS transistors. This study presents a 800-MHz 28.8-mW 8-bit carry look-ahead adder (CLA) using ANT logic implemented on chip. FinFET technology is utilized to improve carrier mobility and increase device speed. R-C parasitic capacitance in FinFET devices is considered in the analysis of the delay time for the 8-bit CLA to improve PDP (power-delay product). The proposed design is implemented in 16-nm FinFET process with core area of 206.403 \(\times \) 152.506 \(\upmu \)m\(^2\). It has the lowest normalized PDP at 60 pF load by far.

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Acknowledgements

This study was funded partially by the Ministry of Science and Technology, Taiwan under Grant Nos. MOST 109-2218-E-110-007-, MOST 109-2221- E-230-007-, MOST 109-2224- E-110-001- and MOST 110-2218-E-110-008-. In addition, the authors would also like to convey their heartfelt thanks to Taiwan Semiconductor Research Institute (TSRI) of National Applied Research Laboratories (NARL), Taiwan, for chip fabrication and EDA tool assistance.

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Author notes

  1. Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino and Tzung-Je Lee have contributed equally to this work.

Authors and Affiliations

  1. Department of Electrical Engineering, National Sun Yat-Sen University, No. 70 Lian-Hai Road, Gushan District, Kaohsiung, 80424, Taiwan

    Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino & Tzung-Je Lee

  2. Institute of Undersea Technology, National Sun Yat-Sen University, No. 70 Lian-Hai Road, Gushan District, Kaohsiung, 80424, Taiwan

    Chua-Chin Wang

  3. Department of Electronics Engineering, Batangas State University - The National Engineering University, Alangilan, Batangas, 4200, Philippines

    Ralph Gerard B. Sangalang

  4. Department of Electronics Engineering, Technological University of the Philippines, Ayala Boulevard, Ermita, Manila, 1000, Philippines

    Lean Karlo S. Tolentino

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  1. Chua-Chin Wang
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Wang, CC., Jose, O.L.J.A., Yang, WS. et al. A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. Circuits Syst Signal Process 42, 2283–2304 (2023). https://doi.org/10.1007/s00034-022-02212-2

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