Skip to main content
SpringerLink
Log in

Exact Settling Performance Design for CMOS Three-Stage Nested-Miller-Compensated Amplifiers

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

The settling performance design of operational amplifiers is an important issue in discrete-time system applications. Most of the currently existing approaches achieve settling time-oriented design based on an approximate analytical transfer function model, and the result is inaccurate. A method for the exact settling performance-driven design of three-stage nested-Miller-compensated CMOS amplifiers is proposed in this paper. With the user-specified settling time at a certain accuracy level, this method finds the optimal solution by a two-step strategy, where the parameters of the compensation network are first solved from the equations formulated based on the minimal settling condition, and then the transconductance of the last stage is adjusted automatically according to the targeted settling time. The accuracy of the method is guaranteed by the use of the SPICE simulation of the settling waveform in the entire procedure. When the process variations are considered, an accurate worst-case design method is further developed. The method also features high efficiency compared with conventional optimization-based approaches. Experimental results of the simulated design in a 90 nm technology are provided to validate the effectiveness of the method.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15

Similar content being viewed by others

Data Availability

The datasets generated in this study are available from the corresponding author on reasonable request.

References

  1. S.R. Afrancheh, et al, Design procedure for settling time minimization in three-stage RNMC amplifiers, in IEEE EUROCON—International Conference on Computer as a Tool (Lisbon, Portugal, 2011). https://doi.org/10.1109/EUROCON.2011.6174587

  2. H. Aminzadeh, Three-stage nested-Miller-compensated operational amplifiers: analysis, design, and optimization based on settling time. Int. J. Circuit Theory Appl. 39, 573–587 (2011). https://doi.org/10.1002/cta.663

    Article  Google Scholar 

  3. E. Cabrera-Bernal et al., 0.7-V three-stage class-AB CMOS operational transconductance amplifier. IEEE Trans. Circuits Syst. I 63(11), 1807–1815 (2016). https://doi.org/10.1109/TCSI.2016.2597440

    Article  Google Scholar 

  4. S.O. Cannizzaro et al., Design procedures for three-stage CMOS OTAs with nested-Miller compensation. IEEE Trans. Circuits Syst. I 54(5), 933–940 (2007). https://doi.org/10.1109/TCSI.2007.895520

    Article  MathSciNet  Google Scholar 

  5. A.M.L. Canelas, J.M.C. Guilherme, N.C.G. Horta, Yield-aware analog IC design and optimization in nanometer-scale technologies. Springer (2020). https://doi.org/10.1007/978-3-030-41536-5

    Article  Google Scholar 

  6. S.S. Chong, P.K. Chan, Cross feedforward cascode compensation for low-power three-stage amplifier with large capacitive load. IEEE J. Solid State-Circuits 47(9), 2227–2234 (2012). https://doi.org/10.1109/JSSC.2012.2194090

    Article  Google Scholar 

  7. A. Garimella, M.W. Rashid, P.M. Furth, Reverse nested Miller compensation using current buffers in a three-stage LDO. IEEE Trans. Circuits Syst. II 57(4), 250–254 (2010). https://doi.org/10.1109/TCSII.2010.2043401

    Article  Google Scholar 

  8. G. Giustolisi, G. Palumbo, Three-stage dynamic-Biased CMOS amplifier with a robust optimization of the settling time. IEEE Trans. Circuits Syst. I 62(11), 2641–2651 (2015). https://doi.org/10.1109/TCSI.2015.2476396

    Article  MathSciNet  MATH  Google Scholar 

  9. G. Giustolisi, G. Palumbo, Robust design of CMOS amplifiers oriented to settling-time specification. Int. J. Circuit Theory Appl. 45(10), 1329–1348 (2017). https://doi.org/10.1002/cta.2309

    Article  Google Scholar 

  10. G. Giustolisi, G. Palumbo, Design of CMOS three-stage amplifiers for near-to-minimum settling-time. Microelectron. J. 107, 104939 (2021). https://doi.org/10.1016/J.MEJO.2020.104939

    Article  Google Scholar 

  11. G. Giustolisi, G. Palumbo, Design of three-stage OTA based on settling-time requirements including large and small signal behavior. IEEE Trans. Circuits Syst. I 68(3), 998–1011 (2021). https://doi.org/10.1109/TCSI.2020.3044454

    Article  Google Scholar 

  12. G. Giustolisi, G. Palumbo, Efficient design strategy for optimizing the settling time in three-stage amplifiers including small-and large-signal behavior. Electronics 10, 612 (2021). https://doi.org/10.3390/electronics10050612

    Article  Google Scholar 

  13. G. Giustolisi, G. Palumbo, Settling-time oriented OTA design through the approximation of the ideal delay. IEEE Int. Sympos. Circuits Syst. (2018). https://doi.org/10.1109/ISCAS.2018.8351087

    Article  Google Scholar 

  14. G. Giustolisi, G. Palumbo, Bessel like compensation of three stage operational transconductance amplifiers. Int. J. Circuit Theory Appl. 46(4), 729–747 (2018). https://doi.org/10.1002/cta.2438

    Article  Google Scholar 

  15. S. Golabi, M. Yavari, Design of CMOS three-stage amplifiers for fast-settling switched-capacitor circuits. Analog Integr. Circ. Sig. Process 80, 195–208 (2014). https://doi.org/10.1007/s10470-014-0332-y

    Article  Google Scholar 

  16. A.D. Grasso et al., Design methodology of subthreshold three-stage CMOS OTAs suitable for ultra-low-power low-area and high driving capability. IEEE Trans. Circuits Syst. I 62(6), 1453–1462 (2015). https://doi.org/10.1109/TCSI.2015.2411796

    Article  MathSciNet  MATH  Google Scholar 

  17. A.D. Grasso, G. Palumbo, S. Pennisi, Advances in reversed nested Miller compensation. IEEE Trans. Circuits Syst. I 54(7), 1459–1470 (2007). https://doi.org/10.1109/TCSI.2007.900170

    Article  Google Scholar 

  18. S. Guo, H. Lee, Single-capacitor active-feedback compensation for small-capacitive-load three-stage amplifiers. IEEE Trans. Circuits Syst. II 56(10), 758–762 (2009). https://doi.org/10.1109/TCSII.2009.2027954

    Article  Google Scholar 

  19. P.G.A. Jespers, B. Murmann, Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables (Cambridge University Press, Cambridge, 2017). https://doi.org/10.1017/9781108125840.008

    Book  MATH  Google Scholar 

  20. T. Kulej, F. Khateb, 0.3-V 98-dB Rail-to-Rail OTA in 0.18um CMOS. IEEE Access 8, 27459–27467 (2020). https://doi.org/10.1109/ACCESS.2020.2972067

    Article  Google Scholar 

  21. S. Liu, Z. Zhu, J. Wang, L. Liu, Y. Yang, A 1.2-V 2.41-GHz three stage CMOS OTA with efficient frequency compensation technique. IEEE Trans. Circuits Syst. I 66(1), 20–30 (2019). https://doi.org/10.1109/TCSI.2018.2852334

    Article  Google Scholar 

  22. T. McConaghy et al., Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide (Springer, New York, 2013)

    Book  Google Scholar 

  23. R. Nguyen, B. Murmann, The design of fast-settling three-stage amplifiers using the open-loop damping factor as a design parameter. IEEE Trans. Circuits Syst. I 57(6), 1244–1254 (2010). https://doi.org/10.1109/TCSI.2009.2031763

    Article  MathSciNet  Google Scholar 

  24. G. Palumbo, S. Pennisi, Design methodology and advances in nested-Miller compensation. IEEE Trans. Circuits Syst. I 49(7), 893–902 (2002). https://doi.org/10.1109/TCSI.2002.800463

    Article  Google Scholar 

  25. A. Pugliese, G. Cappuccino, G. Cocorullo, Nested-Miller compensation capacitors sizing rules for fast settling amplifiers design. Electron. Lett. 41(10), 573–575 (2005). https://doi.org/10.1049/el:20050398

    Article  Google Scholar 

  26. A. Pugliese, G. Cappuccino, G. Cocorullo, Design procedure for settling time minimization in three-stage nested-Miller amplifiers. IEEE Trans. Circuits Syst. II 55(1), 1–5 (2008). https://doi.org/10.1109/TCSII.2007.906086

    Article  Google Scholar 

  27. A. Pugliese et al., Settling time optimization for three-stage CMOS amplifier topologies. IEEE Trans. Circuits Syst. I 56(12), 2569–2582 (2009). https://doi.org/10.1109/TCSI.2009.2017133

    Article  MathSciNet  MATH  Google Scholar 

  28. W. Qu et al., Design-oriented analysis for Miller compensation and its application to multistage amplifier design. IEEE J. Solid State Circuits 52(2), 517–527 (2017). https://doi.org/10.1109/JSSC.2016.2619677

    Article  Google Scholar 

  29. M. Sengupta et al., Application-specific worst case corners using response surfaces and statistical models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), 1372–1380 (2005). https://doi.org/10.1109/TCAD.2005.852037

    Article  Google Scholar 

  30. S. Seth, B. Murmann, Settling time and noise optimization of a three-stage operational transconductance amplifier, in IEEE International Symposium on Circuits and Systems (2012), pp. 205–208. https://doi.org/10.1109/ISCAS.2012.6271684

  31. M. Tan, W.-H. Ki, A cascode Miller-compensated three-stage amplifier with local impedance attenuation for optimized complex-pole control. IEEE J. Solid State-Circuits 50(2), 440–449 (2015). https://doi.org/10.1109/JSSC.2014.2364037

    Article  Google Scholar 

  32. Z. Yan et al., A 0.016-mm 144-μW three-stage amplifier capable of driving 1-to-15 nF capacitive load with>0.95-MHz GBW. IEEE J. Solid State-Circuits 48(2), 527–540 (2013). https://doi.org/10.1109/JSSC.2012.2229070

    Article  Google Scholar 

  33. H. Zhang, et al, Efficient design-specific worst-case corner extraction for integrated circuits, in Proceedings of the IEEE/ACM Design Automation Conference (2009), pp. 386–389. https://doi.org/10.1145/1629911.1630013

Download references

Author information

Authors and Affiliations

  1. School of Electronics and Information Engineering, Hangzhou Dianzi University, Zhejiang, 310018, China

    Wang Xue, Yushun Guo, Yuliang Zhang & Chang Shu

Authors
  1. Wang Xue
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Yushun Guo
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yuliang Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Chang Shu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Yushun Guo.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Xue, W., Guo, Y., Zhang, Y. et al. Exact Settling Performance Design for CMOS Three-Stage Nested-Miller-Compensated Amplifiers. Circuits Syst Signal Process 42, 1327–1351 (2023). https://doi.org/10.1007/s00034-022-02172-7

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-022-02172-7

Keywords

Search

Navigation