Abstract
Artificial neural network (ANN) is widely used in modern engineering applications. The decision on the number of layers and the number of nodes per layer in the ANN or the capacity of the ANN is always a non-trivial. The wrong decision on the capacity of the ANN causes underfit or overfit. This paper proposes various versatile or flexible hardware architectures of multilayer perceptron (MLP)-based neural network, where the number of layers and the number of nodes per layer can be changed with respect to the requirement of the application by avoiding underfit or overfit. Also, the weights of the each node of the MLP can be fixed by the training phase. While the network has being trained, we can change the architecture of the MLP without affecting the accuracy. All the proposed and existing hardware designs of ANNs are implemented with 45 nm CMOS technology. The proposed high throughput design with 3 layers and 512 nodes per layer achieves \(53.8\%\) of improvement in the throughput as compared with the existing technique.
Similar content being viewed by others
Data Availability
All data generated or analyzed during this study are included in this published article and its supplementary information files.
References
A. Ardakani, C. Condo, M. Ahmadi, W.J. Gross, An architecture to accelerate convolution in deep neural networks. IEEE Trans. Circuits Syst. I Regul. Pap. 65(4), 1349–1362 (2018). https://doi.org/10.1109/TCSI.2017.2757036
M. Arvandi, S. Wu, A. Sadeghian, On the use of recurrent neural networks to design symmetric ciphers. IEEE Comput. Intell. Mag. 3(2), 42–53 (2008). https://doi.org/10.1109/MCI.2008.919075
M.A.M. Basiri, Flexible adaptive FIR filter designs using LMS algorithm, in 23rd International Symposium on VLSI Design and Test (VDAT), Communications in Computer and Information Science. Springer 1066, 61–71 (2019). https://doi.org/10.1007/978-981-32-9767-8_6
M.A.M. Basiri, N.M. Sk, An efficient VLSI architecture for lifting based 1D/2D-discrete wavelet transform. Microprocess. Microsyst. 47, 404–418 (2016). https://doi.org/10.1016/j.micpro.2016.08.007
M.A.M. Basiri, N.M. Sk, An efficient hardware based higher radix floating point MAC design. ACM Trans. Design Autom. Electron. Syst. 20(1), 151–1525 (2014). https://doi.org/10.1145/2667224
M.A.M. Basiri, S.K. Shukla, Flexible VLSI architectures for Galois field multipliers. Integr. VLSI J. 59, 109–124 (2017). https://doi.org/10.1016/j.vlsi.2017.06.009
R. Cai, A. Ren, N. Liu, C. Ding, L. Wang, X. Qian, M. Pedram, Y. Wang, VIBNN: hardware acceleration of Bayesian neural networks, in ACM International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 476–488 (2018). https://doi.org/10.1145/3296957.3173212
E. Casseau, B.L. Gal, Design of multi-mode application-specific cores based on high-level synthesis. Integr. VLSI J. 45, 9–21 (2012). https://doi.org/10.1016/j.vlsi.2011.07.003
L. Chen, K.H. Li, C.Y. Huang, Y.K. Lai, Analysis and architecture design of multi-transform architecture for H.264/AVC intra frame coder, in IEEE International Conference on Multimedia and Expo, pp. 145–148 (2008). https://doi.org/10.1109/ICME.2008.4607392
T. Chen, Z. Du, N. Sun, J. Wang, C. Wu, Y. Chen, O. Temam, DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning, in ACM International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 269–283 (2014). https://doi.org/10.1145/2654822.2541967
S. Fu, B.X. Lu, Y.H. Pan, J.H. Shen, R.J. Chen, Architecture design of reconfigurable Reed-Solomon error correction codec, in IEEE International Conference on Advanced Infocomm Technology (ICAIT), pp. 1–2 (2013). https://doi.org/10.1109/ICAIT.2013.6621568
A. Geron, Chapter 1. Introduction to artificial ANNs, O’Reilly Learning Platform. https://www.oreilly.com/library/view/neural-networks-and/9781492037354/ch01.html
A. Gomperts, A. Ukil, F. Zurfluh, Development and implementation of parameterized FPGA-based general purpose neural networks for online applications. IEEE Trans. Industr. Inf. 7(1), 78–89 (2011). https://doi.org/10.1109/TII.2010.2085006
R. Gonzalez, B.M. Gordon, M.A. Horowitz, Supply and threshold voltage scaling for low power CMOS. IEEE J. Solid State Circuits 32(8), 1210–1216 (1997). https://doi.org/10.1109/4.604077
M.A. Kon, L. Plaskota, Information complexity of neural networks. Neural Netw. 13(3), 365–375 (2000). https://doi.org/10.1016/S0893-6080(00)00015-0
S.Y. Kung, J.N. Hwang, Digital VLSI architectures for neural networks, in IEEE International Symposium on Circuits and Systems, pp. 445–448 (1989). https://doi.org/10.1109/ISCAS.1989.100386
T. Murofushi, T. Dobashi, M. Iwahashi, H. Kiya, An integer tone mapping operation for HDR images in openexr with denormalized numbers, in IEEE International Conference on Image Processing (ICIP), pp. 4497–4501 (2014). https://doi.org/10.1109/ICIP.2014.7025912
E.M. Ortigosa, A. Canas, E. Ros, P.M. Ortigosa, S. Mota, J. Diaz, Hardware description of multi-layer perceptrons with different abstraction levels. Microprocess. Microsyst. 30, 435–444 (2006). https://doi.org/10.1016/j.micpro.2006.03.004
S. Qian, H. Liu, C. Liu, S. Wu, H.S. Wong, Adaptive activation functions in convolutional neural networks. Neurocomputing 272, 204–212 (2018). https://doi.org/10.1016/j.neucom.2017.06.070
A. Savich, M. Moussa, S. Areibi, A scalable pipelined architecture for real-time computation of MLP-BP neural networks. Microprocess. Microsyst. 36, 138–150 (2012). https://doi.org/10.1016/j.micpro.2010.12.001
G. Serpen, Z. Gao, Complexity analysis of multilayer perceptron neural network embedded into a wireless sensor network. Proc. Comput. Sci. 36, 192–197 (2014). https://doi.org/10.1016/j.procs.2014.09.078
M.K. Song, H.S. Won, M.H. Kong, Architecture for decoding adaptive Reed-Solomon codes with varying block length, in International Conference on Consumer Electronics, pp. 298–299 (2002). https://doi.org/10.1109/TCE.2002.1037052
V. Sze, Y.H. Chen, T.J. Yang, J.S. Emer, Efficient processing of deep neural networks: a tutorial and survey. Proc. IEEE 105(12), 2295–2329 (2017). https://doi.org/10.1109/JPROC.2017.2761740
The number of hidden layers, Heaton Research (2017). https://www.heatonresearch.com/2017/06/01/hidden-layers.html
S.S. Tirumala, A. Narayanan, Transpositional neurocryptography using deep learning, in ACM International Conference on Information Technology, pp. 330–334 (2017). https://doi.org/10.1145/3176653.3176736
M. Turcanik, Using recurrent neural network for hash function generation, in IEEE International Conference on Applied Electronics (AE), pp. 1–5 (2017). https://doi.org/10.23919/AE.2017.8053625
M. Valle, Analog VLSI implementation of artificial artificial neural networks with supervised on-chip learning. Analog Integr. Circ. Sig. Process 33(3), 263–287 (2002). https://doi.org/10.1023/A:1020717929709
P. Vijayaraghavan, M. Sra, Handwritten Tamil recognition using a convolutional neural network, in International Conference on Information, Communication, Engineering and Technology, pp. 1–7 (2004). https://alumni.media.mit.edu/sra/tamil_cnn.pdf
Z. Yang, A. Srivastava, Value-driven synthesis for neural network ASICs, in ACM International Symposium on Low Power Electronics and Design, pp. 1–6 (2018). https://doi.org/10.1145/3218603.3218634
A. Zakerolhosseini, M. Nikooghadam, Low-power and high-speed design of a versatile bit-serial multiplier in finite fields \(GF(2^m)\). IEEE International Conference on Communication and Signal Processing, Integration, the VLSI Journal 46(2), 211–217 (2013). https://doi.org/10.1016/j.vlsi.2012.03.001
Funding
No funding agency is associated with the work mentioned in this article.
Author information
Authors and Affiliations
Contributions
MA Basiri M contributed to conceptualization, methodology, software, validation, formal analysis, investigation, resources, data curation, writing—original draft preparation, writing—review and editing, visualization, supervision, project administration, and funding acquisition. The author has read and agreed to the published version of the manuscript.
Corresponding author
Ethics declarations
Conflict of interest
The author declares no conflict of interest.
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Basiri, M.M.A. Versatile Architectures of Artificial Neural Network with Variable Capacity. Circuits Syst Signal Process 41, 6333–6353 (2022). https://doi.org/10.1007/s00034-022-02087-3
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-022-02087-3