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Compact Floating Dual Memelement Emulator Employing VDIBA and OTA: A Novel Realization

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Abstract

The aim of this work is to report a very compact floating memelement emulator that can realize two memelements (memristor and meminductor). Both realized memelements can be used in incremental as well as the decremental mode of operation. The presented emulator is based on a single dual-output operational transconductance amplifier and a voltage differencing inverted buffered amplifier along with two grounded passive elements and two external MOS transistors only. The desired memelement function can be achieved by just selecting a grounded impedance Z1 as C1 and R1. Overall CMOS implementation of the proposed circuit requires just twenty CMOS transistors. The emulator has a fully symmetric floating structure (incoming and outgoing currents are exactly equal and opposite in magnitude) and provides complete electronic control over the realized memelements behavior (over both time-dependent and time-independent parts). The developed circuit can be validated through presented simulation results generated in PSPICE using the 0.18 µm CMOS technology. The results verify that behavior of both the realized memelements can be obtained satisfactorily up to MHz range of frequency. The applicability of the realized meminductor behavior is shown in the electrical equivalent network designed for mimicking an Amoeba response for the temperature change, while the emulated memristor function has been validated by employing it in the exhibition of associative learning behavior using the depicted circuit. The given simulator circuit is also implemented using commercial ICs and simulation results are presented.

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  1. Department of Electronics and Communication Engineering, NIT Jamshedpur, Jamshedpur, India

    Kapil Bhardwaj & Mayank Srivastava

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  1. Kapil Bhardwaj
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Correspondence to Mayank Srivastava.

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Bhardwaj, K., Srivastava, M. Compact Floating Dual Memelement Emulator Employing VDIBA and OTA: A Novel Realization. Circuits Syst Signal Process 41, 5933–5967 (2022). https://doi.org/10.1007/s00034-022-02067-7

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