Abstract
This paper investigates a novel highly stable and robust single-ended 10T SRAM cell appropriate for low-power portable applications. The cell core of the proposed design is a combination of a normal inverter with a stacked NMOS transistor and a Schmitt-trigger (ST) inverter with a double-length pull-up transistor. This improves hold stability and leakage power dissipation. The read and write operations of the proposed cell are performed with the aid of separated paths and bitlines, lowering power consumption. The strong cell core and decoupled read path eliminate the read-disturbance issue in the proposed cell, resulting in read static noise margin (RSNM) enhancement. Furthermore, the feedback-cutting write-assist technique used in the proposed design mitigates the writing ‘1’ issue; consequently, write static noise margin (WSNM)/write margin (WM) improves. To prove the superiority of the proposed SRAM cell in various performance metrics, it is compared with state-of-the-art SRAM cells, introduced as 6T, TG9T, 10T-P1, and SB11T, using HSPICE and 16-nm CMOS technology node taking into consideration the impact of the severe process, voltage, and temperature (PVT) variations. Obtained results at VDD = 0.7 V show that the proposed design offers the highest HSNM/RSNM/WSNM (or WM). The read/write delay of the proposed cell is 3.92X/2.37X higher than that of the 6T SRAM cell due to its single-ended reading/writing structure. However, in terms of power consumption, the proposed cell exhibits 1.64X/1.54X lower than that of 6T SRAM cell. Though the proposed cell occupies a 1.24X higher area compared with the 6T SRAM cell due to its higher count of transistor, it shows the highest proposed figure of merit among all the studied SRAM cells, which is 26.90X higher than that of 6T SRAM cell.
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References
E. Abbasian, M. Gholipour, A variation-aware design for storage cells using Schottky-barrier-type GNRFETs. J. Comput. Electron. 19, 987–1001 (2020). https://doi.org/10.1007/s10825-020-01529-y
E. Abbasian, M. Gholipour, Design of a Schmitt-Trigger-based 7T SRAM cell for variation resilient low-energy consumption and reliable internet of things applications. AEU-Int. J. Electron. Commun. 138, 153899 (2021). https://doi.org/10.1016/j.aeue.2021.153899
E. Abbasian, M. Gholipour, Single-ended half-select disturb-free 11T static random access memory cell for reliable and low power applications. Int. J. Circuit Theory Appl. 49(4), 970–989 (2021). https://doi.org/10.1002/cta.2954
E. Abbasian, M. Gholipour, A low-leakage single-bitline 9T SRAM cell with read-disturbance removal and high writability for low-power biomedical applications. Int. J. Circuit Theory Appl. (2022). https://doi.org/10.1002/cta.3231
E. Abbasian, M. Gholipour, F. Izadinasab, Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design. Int. J. Circuit Theory Appl. 49(11), 3630–3652 (2021). https://doi.org/10.1002/cta.3108
E. Abbasian, S. Birla, M. Gholipour, A 9T high-stable and Low-Energy Half-Select-Free SRAM Cell Design using TMDFETs. Analog Integr. Circuit Sig. Process. 11, 1–9 (2022). https://doi.org/10.1007/s10470-022-02036-9
E. Abbasian, S. Birla, M. Gholipour, Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM. Microelectron. J. (2022). https://doi.org/10.1016/j.mejo.2022.105427
E. Abbasian, M. Gholipour, S. Birla, A single-bitline 9T SRAM for low-power near-threshold operation in FinFET technology. Arab. J. Sci. Eng. (2022). https://doi.org/10.1007/s13369-022-06821-6
E. Abbasian, F. Izadinasab, M. Gholipour, A reliable low standby power 10T SRAM cell with expanded static noise margins. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4), 1606–1616 (2022). https://doi.org/10.1109/TCSI.2021.3138849
E. Abbasian, E. Mani, M. Gholipour, M. Karamimanesh, M. Sahid, A. Zaidi, A Schmitt-Trigger-based low-voltage 11 T SRAM cell for low-leakage in 7-nm FinFET technology. Circuits Syst. Signal Process. 41, 3081–3105 (2022). https://doi.org/10.1007/s00034-021-01950-z
S. Ahmad, M.K. Gupta, N. Alam, M. Hasan, Single-ended Schmitt-trigger-based robust low-power SRAM cell. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(8), 2634–2642 (2016). https://doi.org/10.1109/TVLSI.2016.2520490
S. Ahmad, M.K. Gupta, N. Alam, M. Hasan, Low leakage single bitline 9T (SB9T) static random access memory. Microelectron. J. 62, 1–11 (2017). https://doi.org/10.1016/j.mejo.2017.01.011
S. Ahmad, B. Iqbal, N. Alam, M. Hasan, Low leakage fully half-select-free robust SRAM cells with BTI reliability analysis. IEEE Trans. Device Mater. Reliab. 18(3), 337–349 (2018). https://doi.org/10.1109/TDMR.2018.2839612
D. Anh-Tuan, J.Y.S. Low, J.Y.L. Low, Z.-H. Kong, X. Tan, K.-S. Yeo, An 8T differential SRAM with improved noise margin for bit-interleaving in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 58, 1252–1263 (2011). https://doi.org/10.1109/TCSI.2010.2103154
L. Chang, D.M. Fried, J. Hergenrother, J.W. Sleight, R.H. Dennard, R.K. Montoye, et al., Stable SRAM cell design for the 32 nm node and beyond, in Dig. Tech. Pap. 2005 Symp. VLSI Technol. 2005 (2005), pp. 128–129. https://doi.org/10.1109/.2005.1469239.
K. Cho, J. Park, T.W. Oh, S.-O. Jung, One-Sided Schmitt-Trigger-based 9T SRAM Cell for near-threshold operation. IEEE Trans. Circuits Syst. I Regul. Pap. 67(5), 1551–1561 (2020). https://doi.org/10.1109/TCSI.2020.2964903
S. Gupta, K. Gupta, B.H. Calhoun, N. Pandey, Low-power near-threshold 10T SRAM bit cells with enhanced data-independent read port leakage for array augmentation in 32-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66(3), 978–988 (2018). https://doi.org/10.1109/TCSI.2018.2876785
Y. He, J. Zhang, X. Wu, X. Si, S. Zhen, B. Zhang, A half-select disturb-free 11T SRAM cell with built-in write/read-assist scheme for ultralow-voltage operations. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27(10), 2344–2353 (2019). https://doi.org/10.1109/TVLSI.2019.2919104
M.R. Jan, C. Anantha, N. Borivoje, Digital integrated circuits—a design perspective (Prentice-Hall, Upper Saddle River, 2003)
J.P. Kulkarni, K. Roy, Ultralow-voltage process-variation-tolerant Schmitt-trigger-based SRAM design. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(2), 319–332 (2012). https://doi.org/10.1109/TVLSI.2010.2100834
J.P. Kulkarni, K. Kim, K. Roy, A 160 mV robust Schmitt trigger based subthreshold SRAM. IEEE J. Solid-State Circuits 42(10), 2303–2313 (2007). https://doi.org/10.1109/JSSC.2007.897148
R. Lorenzo, R. Pailly, Single bit-line 11T SRAM cell for low power and improved stability. IET Comput. Digit. Tech. 14(3), 114–121 (2020). https://doi.org/10.1049/iet-cdt.2019.0234
N. Maroof, B.-S. Kong, 10T SRAM using Half-VDD precharge and row-wise dynamically powered read port for low switching power and ultralow RBL leakage. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(4), 1193–1203 (2016). https://doi.org/10.1109/TVLSI.2016.2637918
M. Nabavi, M. Sachdev, A 290-mV, 3.34-MHz, 6T SRAM with pMOS access transistors and boosted wordline in 65-nm CMOS technology. IEEE J. Solid-State Circuits 53(2), 656–667 (2017). https://doi.org/10.1109/JSSC.2017.2747151
D. Nayak, D.P. Acharya, K. Mahapatra, A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor. AEU-Int. J. Electron. Commun. 74, 192–197 (2017). https://doi.org/10.1016/j.aeue.2017.02.012
T.W. Oh, H. Jeong, K. Kang, J. Park, Y. Yang, S.-O. Jung, Power-gated 9T SRAM cell for low-energy operation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(3), 1183–1187 (2016). https://doi.org/10.1109/TVLSI.2016.2623601
S. Pal, S. Bose, W.-H. Ki, A. Islam, Characterization of half-select free write assist 9T SRAM cell. IEEE Trans. Electron Devices 66(11), 4745–4752 (2019). https://doi.org/10.1109/TED.2019.2942493
Predictive Technology Model (PTM), [Online], Available: http://ptm.asu.edu/.
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This research was funded by the Babol Noshirvani University of Technology, under research Grant No. P/M/1108.
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Abbasian, E., Gholipour, M. Design of a Highly Stable and Robust 10T SRAM Cell for Low-Power Portable Applications. Circuits Syst Signal Process 41, 5914–5932 (2022). https://doi.org/10.1007/s00034-022-02054-y
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DOI: https://doi.org/10.1007/s00034-022-02054-y