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A Novel Reconfigurable Analog VLSI Architecture of M-point DFT Using Complex Matrix Multiplier and Graph-Based Signal Routing Method

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Abstract

A current-mode reconfigurable architecture for M-point discrete Fourier transform with a complex vector-matrix multiplication method has been presented along with a signal routing algorithm. The circuit for DFT computation of any length can be modeled using this approach. It provides improved performance over other analog circuits using divide-and-conquer algorithms. This architecture consists of two stages: a switched current mirror replicator (SCMR) and the reconfigurable vector-matrix multiplier (VMM). With the analog–digital combined multiplier tuning, precise computation becomes possible. The novel graph-based signal routing algorithm has been proposed to manage multiplier resources efficiently. During 16-point DFT processing, the average accuracy of about \(\pm 0.7\%\) was found at the power consumption of 28.3mW with a processing delay of 4.9\(\mu \)s. The architecture has been modeled with a 65nm CMOS process operating at a 1V power supply.

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Data Availability

This article does not include any specific data set for the validation of proposed theoretical model. However, data generated from the analysis/computation may be made available by the corresponding author on request.

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Acknowledgements

The authors would like to thank MHRD, Govt. of India, for sponsoring this research Work.

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  1. Department of Electronics and Telecommunication Engineering, Indian Institute of Engineering Science and Technology Shibpur, Howrah, India

    Anirban Ganguly & Ayan Banerjee

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  1. Anirban Ganguly
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Ganguly, A., Banerjee, A. A Novel Reconfigurable Analog VLSI Architecture of M-point DFT Using Complex Matrix Multiplier and Graph-Based Signal Routing Method. Circuits Syst Signal Process 41, 5201–5225 (2022). https://doi.org/10.1007/s00034-022-02030-6

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