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An Area-Efficient Majority Logic-Based Approximate Adders with Low Delay for Error-Resilient Applications

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Abstract

This paper presents two new inexact sum-based 1-bit approximate full adders (AFAs). The proposed 1-bit approximate adders (PAAs), namely PAA1 and PAA2, are derived based on the majority logic. The layouts of PAAs are designed in quantum cellular automata (QCA) technology using the QCADesigner tool. To assess the performance of PAAs, we compare them against the reported AFAs in terms of various design metrics, such as the total area, delay, and performance. The comparison results show that the PAA1 and PAA2, having an area of 0.02 \(\upmu \hbox {m}^{2}\) and 0.04 \(\upmu \hbox {m}^{2}\), provide area savings of 60% and 20%, respectively, compared with the lowest-area AFA reported in the literature. Also, the PAA1 and PAA2 have an equal delay of 0.5 clock cycles, that is, 33.33% less as compared to the AFA with the lowest delay. The designs are analyzed in terms of image quality metrics for image processing applications. Besides area efficiency and delay performance, on average, PAA1 provides the worst PSNR/SNR, while PAA2 provides the best PSNR/SNR compared to the other state-of-the-art approximate adders.

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Authors and Affiliations

  1. Department of Electronics and Communication, Vemana Institute of Technology, Koramangala, Bangalore, 560034, Karnataka, India

    M. C. Parameshwara

  2. Electrical and Electronic Engineering Department, College of Engineering, University of Jeddah, Asfan Road, Jeddah, Makkah, 23890, Saudi Arabia

    Naeem Maroof

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  1. M. C. Parameshwara
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  2. Naeem Maroof
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Correspondence to M. C. Parameshwara.

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Parameshwara, M.C., Maroof, N. An Area-Efficient Majority Logic-Based Approximate Adders with Low Delay for Error-Resilient Applications. Circuits Syst Signal Process 41, 4977–4997 (2022). https://doi.org/10.1007/s00034-022-02014-6

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  • DOI: https://doi.org/10.1007/s00034-022-02014-6

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