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Optimized Split Capacitive Array in 16-Bit SAR ADC with Redundancy

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A Correction to this article was published on 14 February 2023

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Abstract

This paper presents an area-efficient split capacitive array architecture for high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs). The equivalent value method is proposed to adjust the bridge capacitance as an integer value so that the bridge capacitance can match well with the unit capacitance. A split capacitive array with redundancy is utilized in a 16-bit SAR ADC and the total required number of the unit capacitors is only 452. Four proposed static pre-amplifiers enhance the noise performance and the offset performance of the comparator and a proposed dynamic latch enhances the speed performance. As a result, the 180 nm design can achieve a 1 MS/s sampling rate with a single channel. The spurious-free dynamic range is 105.85 dB while the effective number of bits can reach 15.78 bits with a Nyquist-rate input while consuming 32 mW from a 5 V supply. The resultant Schreier and Walden figures of merit are 168 dB and 457 fJ/conversion-step respectively. The proposed SAR ADC occupies an active area of 4200 \(\upmu \mathrm{m}\) by 2200 \(\upmu \mathrm{m}\).

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Authors and Affiliations

  1. School of Electronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu, China

    Hua Fan & Peng Lei

  2. Institute of Electronic and Information Engineering of UESTC in Guangdong, Dongguan, China

    Hua Fan

  3. School of Information Science and Technology, Southwest Jiaotong University, Chengdu, China

    Quanyuan Feng

  4. Department of Precision Instrument, Tsinghua University, Beijing, China

    Qi Wei

Authors
  1. Hua Fan
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  2. Peng Lei
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  3. Quanyuan Feng
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  4. Qi Wei
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Correspondence to Hua Fan or Qi Wei.

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The work of Hua Fan was supported by the National Natural Science Foundation of China (NSFC) under Grant 61771111, supported by Sichuan Provincial Science and Technology Important Projects under Grant 22ZDYF2805, supported by the Open Foundation of the State Key Laboratory of Electronic Thin Films and Integrated Devices under Grant KFJJ202006, and supported by Intelligent Terminal Key Laboratory of Sichuan Province under Grant SCITLAB-1001. The work of Quanyuan Feng was supported by Major Project of the National Natural Science Foundation of China under Grant 62090012.

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Fan, H., Lei, P., Feng, Q. et al. Optimized Split Capacitive Array in 16-Bit SAR ADC with Redundancy. Circuits Syst Signal Process 42, 1264–1278 (2023). https://doi.org/10.1007/s00034-022-01955-2

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  • DOI: https://doi.org/10.1007/s00034-022-01955-2

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