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High-Speed and Area-Efficient Modified Binary Divider

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Abstract

Division is the least commonly used of the four basic arithmetic operations because it is too difficult to utilize. The primitive use of division is an iterative subtraction. In very large-scale integration realization, the redundant representation of partial remainders and quotient digits is used in digit recurrence binary division. Divider modules are frequently used in digital signal processing and image processing applications. The former uses carry save representation for binary floating point division where the number of iterations is large and also occupied more area. The floating point binary division using carry save representation led to extra power consumptions for initialization and quotient digit selection. The idea is to lower the number of cycles in use while also taking up less space. Therefore, the signed-digit floating point binary division using carry increment adder has been proposed. It implies that carry increment adder has carry lookahead adder which is to minimize the propagation delay. The quotient digit selection is slightly varied to reduce the number of iterations. Result analysis shows that the area and delay are reduced compared to the floating point binary division using carry save representation. The proposed adder is suitable for high-speed applications.

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Authors and Affiliations

  1. Department of ECE, Ramco Institute of Technology, Rajapalayam, India

    A. Azhagu Jaisudhan Pazhani

  2. Department of ECE, National Engineering College, Kovilpatti, India

    T. S. Arun Samuel

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  1. A. Azhagu Jaisudhan Pazhani
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  2. T. S. Arun Samuel
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Correspondence to T. S. Arun Samuel.

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Pazhani, A.A.J., Samuel, T.S.A. High-Speed and Area-Efficient Modified Binary Divider. Circuits Syst Signal Process 41, 3350–3371 (2022). https://doi.org/10.1007/s00034-021-01937-w

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  • DOI: https://doi.org/10.1007/s00034-021-01937-w

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