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FPGA Design of a Variable Step-Size Variable Tap Length Denlms Filter with Hybrid Systolic-Folding Structure and Compressor-Based Booth Multiplier for Noise Reduction in Ecg Signal

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Abstract

Electrocardiogram (ECG) is a critical type of biological signal that brings significant data about the patients. The morphological structure of ECG signals is usually distorted by the recording and transmission processes. As a result of this distortion, the proper diagnosis of diseases related to the cardiac system is getting affected. In this paper, a new FPGA design of variable step-size variable tap length delayed error normalized least mean square (VSS-VT-DENLMS) noise removal algorithm is proposed that modifies the weight update equation of DENLMS algorithm by varying the step sizes and the tap lengths simultaneously to find better trade-off among the fast convergence and error tracking. Also, the adaptive filter structure of the proposed VSS-DENLMS is developed by considering both systolic and folding structure with compressor-based booth multiplier for improving the performance in terms of speed and area. The proposed filter design is validated by considering different ECG signals from MIT-BIH Arrhythmia database, and the filtered outputs are investigated using certain performance measures including signal-to-noise ratio (SNR), mean square error (MSE), root-mean-square error (RMSE) and hardware complexity in terms of area and delay. The simulation results illustrate that the proposed filter overtakes existing filters and minimizes hardware complexities, which proves the suitability of this approach on real-time applications of ECG signals.

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Data Availability Statement

The data that support the findings of this study are available from “https://archive.physionet.org/cgi-bin/atm/ATM.” The program of this study will be made available to interested researchers from the corresponding author on reasonable request. Please contact the first author on milonimganatraphd1@gmail.com.

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Authors and Affiliations

  1. Electronics and Communication Engineering Department, Indus University, Ahmedabad, Gujarat, India

    Miloni M. Ganatra

  2. Gujarat Technological University, Ahmedabad, Gujarat, India

    Miloni M. Ganatra

  3. Electronics and Communication Engineering Department, Government Engineering College, Rajkot, Gujarat, India

    Chandresh H. Vithalani

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Correspondence to Miloni M. Ganatra.

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The original online version of this article is revised: The affiliation for Author Miloni M. Ganatra should have been Electronics and Communication Engineering Department, Indus University, Ahmedabad, Gujarat, India and Gujarat Technological University, Gujarat, India.

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Ganatra, M.M., Vithalani, C.H. FPGA Design of a Variable Step-Size Variable Tap Length Denlms Filter with Hybrid Systolic-Folding Structure and Compressor-Based Booth Multiplier for Noise Reduction in Ecg Signal. Circuits Syst Signal Process 41, 3592–3622 (2022). https://doi.org/10.1007/s00034-021-01933-0

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