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Analysis and Design of an Efficient 8-Bit 2b/Cycle SAR ADC with Multiple Calibration Techniques

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Abstract

This paper presents a low-power asynchronous 8-bit 500MS/s 2b/cycle successive-approximation-register (SAR) analog-to-digital converter (ADC) in 40 nm CMOS process. The proposed ADC shows high energy efficiency and good performance against process–voltage–temperature (PVT) variations by a background offset mismatch calibration technique, a supply voltage calibration technique and an efficient 2b/cycle switching scheme. The background offset mismatch calibration eliminates the effect of offset mismatches of the comparator array without any extra phase. The supply voltage calibration is presented to monitor the conversion speed of the ADC and adjust the speed of comparators to ensure the ADC can work properly at different process corners. The improved switching scheme helps cut down the switch times and simplifies the switch logic, which saves 87.8% switching energy compared with conventional VCM-based scheme. The proposed SAR ADC simulated a signal-to-noise plus distortion ratio (SNDR) of 45.8 dB and a spurious-free dynamic range (SFDR) of 55.5 dB for a near-Nyquist input while consuming a total power of 2.59 mW, culminating in a Walden figure of merit (FoM) of 32 fJ/conversion-step.

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Data availability

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

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Acknowledgements

This work is supported by the Science and Technology on Low-Light-Level Night Vision Laboratory (No.61424120503162412005) and Wuhu and Xidian University special fund for industry-university-research cooperation (Project No.: XWYCXY-012020013-HT).

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Authors and Affiliations

  1. School of Microelectronics, Xidian University, Xi’an, 710071, People’s Republic of China

    Yushi Chen, Hualian Tang & Yiqi Zhuang

  2. Science and Technology on Low-Light-Level Night Vision Laboratory, Xi’an, 710076, People’s Republic of China

    Yuan Yuan

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  1. Yushi Chen
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Correspondence to Hualian Tang.

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Chen, Y., Yuan, Y., Tang, H. et al. Analysis and Design of an Efficient 8-Bit 2b/Cycle SAR ADC with Multiple Calibration Techniques. Circuits Syst Signal Process 41, 2541–2565 (2022). https://doi.org/10.1007/s00034-021-01924-1

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  • DOI: https://doi.org/10.1007/s00034-021-01924-1

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