Abstract
This paper explores the design and hardware efficient realization of low complexity filter bank-based reconfigurable channelizers suitable for wireless receivers. The reconfigurability is achieved by deriving a set of non-uniform filter banks with different sampling factor combinations from a low complexity partial cosine modulated uniform filter bank, by combining different number of its neighbouring channels. The hardware complexity comparison of the filter bank channelizer designed by the proposed approach, with the existing works proves that this approach requires less number of multipliers in its realization to extract the same set of communication standards. To reduce the power and complexity of the multipliers needed for the hardware realization of the filter coefficients, an approximation algorithm, which increases the zeros in the binary represented filter coefficients is employed. The synthesis results show that the algorithm offers a considerable reduction in the hardware and power consumptions of the filter bank.
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Acknowledgements
Authors would like to thank the Department of Science & Technology, Government of India for supporting this work under the FIST scheme No. SR/FST/ET-I/2017/68.
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Hareesh, V., Bindiya, T.S. Design of Hardware Efficient Reconfigurable Merged Partial Cosine Modulated Non-uniform Filter Bank Channelizer and its Power Efficient Implementation Using a Novel Approximation Algorithm. Circuits Syst Signal Process 41, 2118–2135 (2022). https://doi.org/10.1007/s00034-021-01877-5
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DOI: https://doi.org/10.1007/s00034-021-01877-5