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A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS

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Abstract

In this work, a dual loop all-digital phase locked loop (ADPLL) is designed to obtain a fast locking, low power and low jitter for SoC and battery-operated applications. The high speed and high-resolution 4-bit flash time to digital converter (TDC) is also proposed to achieve low jitter and fast locking in ADPLL. The flash TDC uses a foreground calibration to make the ADPLL work robustly over PVT variations. In present work, fasting settling time of 1 μs and low power is achieved for proposed ADPLL owing to flash-based TDC and dual loop architecture. The proposed 4-bit flash TDC achieves a resolution of 6 ps. A low-phase noise voltage-controlled oscillator based on inverters is designed to obtain a reduced jitter in ADPLL. The ADPLL is implemented in a 180-nm SCL digital CMOS technology. The achieved phase noise of proposed ADPLL is − 128.2 dBc/Hz at an offset of 100 MHz. At an output frequency of 1.6 GHz, the periodic jitter of ADPLL is 7.8 ps, and power consumption is 6.5 mW.

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Data sharing not applicable to this article as no datasets were generated or analysed during the current study.

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Acknowledgements

The SMDP-VLSI (Phase-III) provides a financial aid for execution of project. The project is being acknowledged gratefully.

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Authors and Affiliations

  1. ECED, Thapar Institute of Engineering and Technology, Patiala, India

    Jagdeep Kaur Sahani, Anil Singh & Alpana Agarwal

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  1. Jagdeep Kaur Sahani
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Correspondence to Anil Singh.

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Sahani, J.K., Singh, A. & Agarwal, A. A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS. Circuits Syst Signal Process 41, 1299–1323 (2022). https://doi.org/10.1007/s00034-021-01861-z

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  • DOI: https://doi.org/10.1007/s00034-021-01861-z

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