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The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures

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Abstract

Over the years, the use of adder compressors has been a promising alternative to reduce power of dedicated hardware architectures. Adder compressors are able to perform several additions in parallel by reusing their internal structure. Many signals and visual processing applications are based on discrete transforms and require butterfly-based architectures (i.e., architectures that perform additions and subtractions sharing the same operands). The butterfly-based structures reduce the savings of the state-of-the-art adder compressors due to the duplication of the hardware. This work extends the results about a new fused adder–subtractor (FAS) 4-2 compressor arithmetic operator. The FAS 4-2 compressor performs the butterfly operation (i.e., add and subtractions) in a single optimized arithmetic operator reusing the internal structure and then increases the power-efficiency of butterfly-based architectures. We propose to fuse both adds and subtractions in a single compact structure showing how to share the internal logic to perform simultaneously both operations. As a case study for a butterfly-based architecture, we employed the sum of absolute transformed differences (SATD) design based on Hadamard transforms (HT) of multiple sizes, where the smallest HTs are reused for the implementation of the largest ones. Synthesis results for a 45 nm CMOS technology show that the FAS 4-2 architecture herein proposed presents power and circuit area savings of about 7.1% and 8.4% when compared to the state-of-the-art circuit which employs two 4-2 adder compressors. Moreover, the full SATD architecture with the proposed FAS 4-2 compressors improves the power-efficiency from 5.8% (i.e., against conventional adder compressors) to 10% on average, when compared to the adder operator automatically inferred by the synthesis tool.

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Data Availability Statement

Data sharing not applicable to this article as no datasets were generated or analyzed during the current study.

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Acknowledgements

The authors would like to thank CNPq, Capes and Fapergs Brazilian agencies for financial support to our research.

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Author notes

  1. Bianca Silveira and Guilherme Paim have contributed equally to this work.

Authors and Affiliations

  1. Graduate Program on Electronic Engineering and Computing, Universidade Católica de Pelotas (UCPel), Pelotas, Brazil

    Bianca Silveira, Rafael dos Santos Ferreira, Cláudio Machado Diniz & Eduardo Antônio César da Costa

  2. Graduate Program in Microelectronics (PGMICRO), Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil

    Guilherme Paim, Brunno Alves Abreu & Sergio Bampi

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  1. Bianca Silveira
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Correspondence to Guilherme Paim.

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Silveira, B., Paim, G., Abreu, B.A. et al. The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures. Circuits Syst Signal Process 41, 1577–1595 (2022). https://doi.org/10.1007/s00034-021-01839-x

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