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32-Gb/s NRZ and 40-Gb/s PAM-4 Transimpedance Amplifier Paralleling with a Differentiator for Bandwidth Enhancement in 90-nm CMOS Technology

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Abstract

In this article, a wide-bandwidth, fully differential transimpedance amplifier (TIA) is implemented in Taiwan Semiconductor Manufacturing Company 90-nm complementary metal–oxide–semiconductor technology. The regulated cascode circuit has low input impedance and is used for the input stage of the TIA. The core amplifier is a fully differential amplifier circuit, paralleling with a differentiator that is capable of enhancing the bandwidth of the TIA. The inductorless TIA has a differential transimpedance gain of 40 dBΩ, a bandwidth of 25.85 GHz, and an average input-referred current noise density of 25 pA/√Hz. The TIA chip has a power consumption of 29 mW with a supply voltage of 1 V, and the chip area is 0.164 mm2. In the chip testing, the 32-Gb/s non-return-to-zero (NRZ) and the 40-Gb/s four-level pulse amplitude modulation (PAM-4) eye diagrams are measured and are sufficiently clear. Our TIA can be applied in a 32-Gb/s NRZ and a 40-Gb/s PAM-4 optical receiver.

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Data Availability

The measured data has been included in this article, and the parts of the design parameters of the circuit components are shown in this article. The structure and detail of the TIA circuit has been presented in this article, and the readers can refer to the content of this article to reproduce this circuit design. The DOI of the relevant references for this work has also been provided in this article.

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Acknowledgements

This work was supported partly by the Taiwan Semiconductor Research Institute and the Taiwan Ministry of Science and Technology, under the contract MOST 109-2224-E-992-001.

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  1. Department of Electronic Engineering, National Kaohsiung University of Science and Technology, Kaohsiung, Taiwan

    Jau-Ji Jou, Tien-Tsorng Shih & Hao-Wen Hsu

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  1. Jau-Ji Jou
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Jou, JJ., Shih, TT. & Hsu, HW. 32-Gb/s NRZ and 40-Gb/s PAM-4 Transimpedance Amplifier Paralleling with a Differentiator for Bandwidth Enhancement in 90-nm CMOS Technology. Circuits Syst Signal Process 41, 621–635 (2022). https://doi.org/10.1007/s00034-021-01826-2

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