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Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root

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Abstract

In this paper, we propose a low-complexity and high-speed VLSI architecture design methodology for complex square root computation using COordinate Rotation DIgital Computer (CORDIC). The proposed methodology is independent of angle computation in the CORDIC unlike the state-of-the-art methodologies. The proposed methodology is modelled in VHDL and synthesized under the TSMC 45-nm CMOS technology @ 1 GHz frequency. The synthesis results show that the proposed design saves 18.39%, 4.06% and 17.26%, 2.56% on chip area and power consumption when compared with the state-of-the-art methodologies without loss in accuracy. The proposed design saves the latency of 16 and 14 clock cycles when compared with the state-of-the-art implementations. The proposed design can process 23.4 and 127.344 billion additional samples per one joule energy when compared with the state-of-the-art designs.

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The data that support the findings of this study are available from the corresponding author on reasonable request.

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Acknowledgements

Authors acknowledge “Indigenous Intelligent and Scalable Neuromorphic Multichip for AI Training and Inference Solutions” project funded by the Ministry of electronics and Information technology (MEITY), Government of India, with Approval No. \(4(7)/2021-ITEA\) dated 8 March 2021.

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  1. Department of Electrical Engineering, Indian Institute of Technology Hyderabad, Hyderabad, India

    Suresh Mopuri & Amit Acharyya

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  1. Suresh Mopuri
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  2. Amit Acharyya
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Correspondence to Amit Acharyya.

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Mopuri, S., Acharyya, A. Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root. Circuits Syst Signal Process 40, 5759–5772 (2021). https://doi.org/10.1007/s00034-021-01738-1

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